Patents by Inventor Ruchi Wadhawan
Ruchi Wadhawan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9761202Abstract: This application relates to performing seamless video transitions at a display panel when a video stream changes resolution and/or scale. The video stream can be provided by a host device to a timing controller (TCON). When a parameter of the video stream is going to change, the host device can cause the TCON to enter a panel self refresh (PSR) mode. During the PSR mode, the TCON can drive the display panel using an image frame stored in a memory of the TCON. Additionally, during the PSR mode, the host device can adjust a scaler and/or resolution associated with the TCON. Once the host device has finished adjusting the TCON, the TCON can exit the PSR mode and the host device can provide a new data stream to the TCON without any apparent display artifacts being output by the display panel.Type: GrantFiled: March 4, 2016Date of Patent: September 12, 2017Assignee: Apple Inc.Inventors: Christopher P. Tann, Ruchi Wadhawan
-
Publication number: 20160267881Abstract: This application relates to performing seamless video transitions at a display panel when a video stream changes resolution and/or scale. The video stream can be provided by a host device to a timing controller (TCON). When a parameter of the video stream is going to change, the host device can cause the TCON to enter a panel self refresh (PSR) mode. During the PSR mode, the TCON can drive the display panel using an image frame stored in a memory of the TCON. Additionally, during the PSR mode, the host device can adjust a scaler and/or resolution associated with the TCON. Once the host device has finished adjusting the TCON, the TCON can exit the PSR mode and the host device can provide a new data stream to the TCON without any apparent display artifacts being output by the display panel.Type: ApplicationFiled: March 4, 2016Publication date: September 15, 2016Inventors: Christopher P. TANN, Ruchi WADHAWAN
-
Patent number: 9262353Abstract: In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.Type: GrantFiled: January 6, 2015Date of Patent: February 16, 2016Assignee: Apple Inc.Inventors: Josh P. de Cesare, Ruchi Wadhawan, Erik P. Machnicki, Mark D. Hayter
-
Publication number: 20150113193Abstract: In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.Type: ApplicationFiled: January 6, 2015Publication date: April 23, 2015Inventors: Josh P. de Cesare, Ruchi Wadhawan, Erik P. Machnicki, Mark D. Hayter
-
Patent number: 8959270Abstract: In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.Type: GrantFiled: December 7, 2010Date of Patent: February 17, 2015Assignee: Apple Inc.Inventors: Josh P. de Cesare, Ruchi Wadhawan, Erik P. Machnicki, Mark D. Hayter
-
Patent number: 8762653Abstract: In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to schedule operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.Type: GrantFiled: October 24, 2013Date of Patent: June 24, 2014Assignee: Apple Inc.Inventors: Sukalpa Biswas, Hao Chen, Ruchi Wadhawan
-
Publication number: 20140052937Abstract: In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to schedule operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.Type: ApplicationFiled: October 24, 2013Publication date: February 20, 2014Applicant: Apple Inc.Inventors: Sukalpa Biswas, Hao Chen, Ruchi Wadhawan
-
Patent number: 8631213Abstract: In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to schedule operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.Type: GrantFiled: September 16, 2010Date of Patent: January 14, 2014Assignee: Apple Inc.Inventors: Sukalpa Biswas, Hao Chen, Ruchi Wadhawan
-
Patent number: 8578079Abstract: In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.Type: GrantFiled: November 6, 2012Date of Patent: November 5, 2013Assignee: Apple Inc.Inventors: Josh P de Cesare, Ruchi Wadhawan, Michael J Smith, Puneet Kumar, Bernard J Semeria
-
Patent number: 8566485Abstract: In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.Type: GrantFiled: August 3, 2012Date of Patent: October 22, 2013Assignee: Apple Inc.Inventors: Dominic Go, Mark D. Hayter, Zongjian Chen, Ruchi Wadhawan
-
Patent number: 8417844Abstract: In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.Type: GrantFiled: May 17, 2012Date of Patent: April 9, 2013Assignee: Apple Inc.Inventors: Dominic Go, Mark D. Hayter, Zongjian Chen, Ruchi Wadhawan
-
Patent number: 8332559Abstract: In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.Type: GrantFiled: March 7, 2012Date of Patent: December 11, 2012Assignee: Apple Inc.Inventors: Josh P. de Cesare, Ruchi Wadhawan, Michael J. Smith, Puneet Kumar, Bernard J. Semeria
-
Publication number: 20120297097Abstract: In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.Type: ApplicationFiled: August 3, 2012Publication date: November 22, 2012Applicant: Apple Inc.Inventors: Dominic Go, Mark D. Hayter, Zongjian Chen, Ruchi Wadhawan
-
Publication number: 20120233360Abstract: In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.Type: ApplicationFiled: May 17, 2012Publication date: September 13, 2012Inventors: Dominic Go, Mark D. Hayter, Zongjian Chen, Ruchi Wadhawan
-
Publication number: 20120167107Abstract: In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.Type: ApplicationFiled: March 7, 2012Publication date: June 28, 2012Inventors: Josh P. de Cesare, Ruchi Wadhawan, Michael J. Smith, Puneet Kumar, Bernard J. Semeria
-
Patent number: 8209446Abstract: In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.Type: GrantFiled: August 30, 2011Date of Patent: June 26, 2012Assignee: Apple Inc.Inventors: Dominic Go, Mark D. Hayter, Zongjian Chen, Ruchi Wadhawan
-
Publication number: 20120144172Abstract: In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.Type: ApplicationFiled: December 7, 2010Publication date: June 7, 2012Inventors: Josh P. de Cesare, Ruchi Wadhawan, Erik P. Machnicki, Mark D. Hayter
-
Patent number: 8176257Abstract: In one embodiment, a cache comprises a data memory comprising a plurality of data entries, each data entry having capacity to store a cache block of data, and a cache control unit coupled to the data memory. The cache control unit is configured to dynamically allocate a given data entry in the data memory to store a cache block being cached or to store data that is not being cache but is being staged for retransmission on an interface to which the cache is coupled.Type: GrantFiled: April 15, 2011Date of Patent: May 8, 2012Assignee: Apple Inc.Inventors: Ruchi Wadhawan, Jason M. Kassoff, George Kong Yiu
-
Patent number: 8156275Abstract: In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.Type: GrantFiled: May 13, 2009Date of Patent: April 10, 2012Assignee: Apple Inc.Inventors: Josh P. de Cesare, Ruchi Wadhawan, Michael J. Smith, Puneet Kumar, Bernard J. Semeria
-
Publication number: 20120072678Abstract: In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to scheduled operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.Type: ApplicationFiled: September 16, 2010Publication date: March 22, 2012Inventors: Sukalpa Biswas, Hao Chen, Ruchi Wadhawan