Abstract: An apparatus and method to reduce bandwidth and latency associated with probabilistic caches.

Abstract: An apparatus and method to reduce bandwidth and latency associated with probabilistic caches.

Abstract: A processor includes a core to execute a transaction with a memory via cache; and cache controller having an index mapper circuit to: identify a physical memory address associated with the transaction and having a plurality of bits; determine, based on the plurality of bits, a first set of bits encoding a tag value, a second set of bits encoding a page index value, and a third set of bits encoding a line index value; determine a mapping function corresponding to the tag value; determine, using the mapping function, a bit-placement order; combine, based on the order, second and third set of bits to form an index; generate, using the index, a mapping from the address to a cache line index value identifying a cache line in the cache; and wherein the cache controller is further to access, using the mapping and in response to the transaction, the cache line.

Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.

Abstract: An embodiment of a semiconductor package apparatus may include technology to identify a nested loop in a set of executable instructions, and determine at runtime if the nested loop is a candidate for cache blocking. Other embodiments are disclosed and claimed.

Abstract: A processor includes a processor core and a cache controller coupled to the processor core. The cache controller is to allocate, for a memory, a plurality of cache entries in a cache, wherein the processor core is to: detect an amount of the memory installed in a computing system and, responsive to detecting less than a maximum allowable amount of the memory for the computing system, direct the cache controller to increase a number of ways of the cache in which to allocate the plurality of cache entries.

Abstract: A processor includes a core to execute a transaction with a memory via cache; and cache controller having an index mapper circuit to: identify a physical memory address associated with the transaction and having a plurality of bits; determine, based on the plurality of bits, a first set of bits encoding a tag value, a second set of bits encoding a page index value, and a third set of bits encoding a line index value; determine a mapping function corresponding to the tag value; determine, using the mapping function, a bit-placement order; combine, based on the order, second and third set of bits to form an index; generate, using the index, a mapping from the address to a cache line index value identifying a cache line in the cache; and wherein the cache controller is further to access, using the mapping and in response to the transaction, the cache line.

Abstract: Techniques are disclosed to identify a frequently-executed region of code during runtime execution of the code, generate initial profiling code for the frequently-executed region of code, cause the initial profiling code to be executed for a minimum number of processing cycles of the computer, and identify replacement candidate store instruction(s) that store a value that is not read by the frequently-executed region of code during execution of the initial profiling code. Replacement candidate load instruction(s) may also be identified that load a value that is not stored or loaded by the frequently-executed region of code during execution of the initial profiling code. Optimized code for the frequently-executed region of code may be generated by replacing each of the replacement candidate store or load instructions(s) with a non-temporal store or load instruction. The optimized code may be executed instead of the frequently-executed region of code during subsequent runtime execution.

Abstract: A processor includes a processing core to execute a transaction with a memory via a cache and a cache controller, associated with the processor, comprising an index mapper circuit to identify a physical memory address associated with the transaction, wherein the physical memory address comprises a plurality of bits, determine, based on the plurality of bits, a first set of bits encoding a tag value, a second set of bits encoding a page index value, and a third set of bits encoding a line index value, determine, based on the tag value, a bit-placement order for combining the second set of bits and the third set of bits, combine, based on the bit-placement order, the second set of bits and the third set of bits to form an index, and generate, based on the index, a mapping from the physical memory address to a cache line index value identifying a cache line in the cache, wherein the processing core is to access, based on the cache line, a memory location referenced by the physical memory address.

Abstract: A processor includes a processor core and a cache controller coupled to the processor core. The cache controller is to allocate, for a memory, a plurality of cache entries in a cache, wherein the processor core is to: detect an amount of the memory installed in a computing system and, responsive to detecting less than a maximum allowable amount of the memory for the computing system, direct the cache controller to increase a number of ways of the cache in which to allocate the plurality of cache entries.

Abstract: An embodiment of a semiconductor package apparatus may include technology to identify a nested loop in a set of executable instructions, and determine at runtime if the nested loop is a candidate for cache blocking. Other embodiments are disclosed and claimed.

Abstract: A processor includes a processor core and a cache controller coupled to the processor core. The cache controller is to allocate, for a memory, a plurality of cache entries in a cache, wherein the processor core is to: detect an amount of the memory installed in a computing system and, responsive to detecting less than a maximum allowable amount of the memory for the computing system, direct the cache controller to increase a number of ways of the cache in which to allocate the plurality of cache entries.

Abstract: In one embodiment, a processor includes: a fetch logic to fetch instructions; a decode logic to decode the instructions; a cache memory; and a control logic to receive a cache filter instruction and responsive to the cache filter instruction enable only a selected portion of a memory address space to be eligible to be cached in the cache memory. The cache filter instruction may indicate the selected portion of the memory address space. Other embodiments are described and claimed.

Abstract: A processor includes a processing core to execute a transaction with a memory via a cache and a cache controller, associated with the processor, comprising an index mapper circuit to identify a physical memory address associated with the transaction, wherein the physical memory address comprises a plurality of bits, determine, based on the plurality of bits, a first set of bits encoding a tag value, a second set of bits encoding a page index value, and a third set of bits encoding a line index value, determine, based on the tag value, a bit-placement order for combining the second set of bits and the third set of bits, combine, based on the bit-placement order, the second set of bits and the third set of bits to form an index, and generate, based on the index, a mapping from the physical memory address to a cache line index value identifying a cache line in the cache, wherein the processing core is to access, based on the cache line, a memory location referenced by the physical memory address.

Abstract: Techniques are disclosed to identify a frequently-executed region of code during runtime execution of the code, generate initial profiling code for the frequently-executed region of code, cause the initial profiling code to be executed for a minimum number of processing cycles of the computer, and identify replacement candidate store instruction(s) that store a value that is not read by the frequently-executed region of code during execution of the initial profiling code. Replacement candidate load instruction(s) may also be identified that load a value that is not stored or loaded by the frequently-executed region of code during execution of the initial profiling code. Optimized code for the frequently-executed region of code may be generated by replacing each of the replacement candidate store or load instructions(s) with a non-temporal store or load instruction. The optimized code may be executed instead of the frequently-executed region of code during subsequent runtime execution.

Abstract: A processor includes a processor core and a cache controller coupled to the processor core. The cache controller is to allocate, for a memory, a plurality of cache entries in a cache, wherein the processor core is to: detect an amount of the memory installed in a computing system and, responsive to detecting less than a maximum allowable amount of the memory for the computing system, direct the cache controller to increase a number of ways of the cache in which to allocate the plurality of cache entries.

Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.

Abstract: Described herein are mechanisms for continuous automatic tuning of code regions for optimal hardware configurations for the code regions. One mechanism automatically tunes the tunable parameters for a demarcated code region by calculating metrics while executing the code region with different sets of tunable parameters and selecting one of the different sets based on the calculated metrics.

Abstract: A mechanism for tracking the control flow of instructions in an application and performing one or more optimizations of a processing device, based on the control flow of the instructions in the application, is disclosed. Control flow data is generated to indicate the control flow of blocks of instructions in the application. The control flow data may include annotations that indicate whether optimizations may be performed for different blocks of instructions. The control flow data may also be used to track the execution of the instructions to determine whether an instruction in a block of instructions is assigned to a thread, a process, and/or an execution core of a processor, and to determine whether errors have occurred during the execution of the instructions.

Abstract: In one embodiment of the invention, a processor comprising an upper level cache and at least one processor core. The at least one processor core includes one or more registers and a plurality of instruction processing stages: a decode unit to decode an instruction requiring an input of a plurality of data elements, wherein a size of each of the plurality of data elements is less than a cache line size of the processor; an execution unit to load the plurality of data elements to the one or more registers of the processor, without loading data elements spatially adjacent to the plurality of data elements or the plurality of data elements in an upper level cache.