Abstract: An integrated semiconductor memory contains a multiplicity of bit line pairs which each comprise a first bit line and a second bit line. Sense amplifiers are each coupled to one of the bit line pairs for evaluating a signal on the first and second bit lines. A data line pair coupled to at least one of the multiplicity of bit line pairs for outputting a datum is furthermore provided. A correction device is connected on the output side to the data line pair or to at least one bit line pair. The device is embodied for feeding a correction signal onto the line pair.

Abstract: An integrated semiconductor memory contains a multiplicity of bit line pairs which each comprise a first bit line and a second bit line. Sense amplifiers are each coupled to one of the bit line pairs for evaluating a signal on the first and second bit lines. A data line pair coupled to at least one of the multiplicity of bit line pairs for outputting a datum is furthermore provided. A correction device is connected on the output side to the data line pair or to at least one bit line pair. The device is embodied for feeding a correction signal onto the line pair.

Abstract: A voltage level converter device for the conversion of an input signal, which is at a first voltage level, into an output signal, which is at a second voltage level that differs from the first voltage level, where the voltage level converter device has at least one transistor, and in which an additional transistor, controlled by a control signal at a voltage level corresponding to that of the input signal, is provided in a current path that is to be accordingly switched on or off when the output signal switches over for switching that path on or off.

Abstract: A voltage level converter device for the conversion of an input signal, which is at a first voltage level, into an output signal, which is at a second voltage level that differs from the first voltage level, where the voltage level converter device has at least one transistor, and in which an additional transistor, controlled by a control signal at a voltage level corresponding to that of the input signal, is provided in a current path that is to be accordingly switched on or off when the output signal switches over for switching that path on or off.

Abstract: An adjustable delay circuit for digital signals includes a series circuit which is disposed between two supply potentials and has at least a first transistor of a first conduction type and second and third transistors of a second conduction type. Control connections of the first and second transistors are connected to a signal input of the delay circuit. One connection of the first transistor, which is remote from the first supply potential, is connected to a signal output. A fourth transistor of the second conduction type is connected in parallel with the third transistor. A first control input is connected to a control connection of the third transistor and a second control input is connected to a control connection of the fourth transistor. The control inputs are used to adjust the delay time of the delay circuit.

Abstract: A circuit apparatus for evaluating a data content of memory cells of an integrated semiconductor memory, which memory cells are disposed along bit lines and word lines. The circuit apparatus has a voltage compensation device with voltage compensation elements which are connected for the purpose of voltage coupling of in each case two neighboring bit lines and which enable compensation for a capacitive coupling between the bit lines.

Abstract: The fuse refresh circuit for semiconductor memories has a set circuit for setting a fuse latch circuit. The fuse latch circuit is set by the set circuit in at least one refresh cycle after a voltage supply has been switched on. During the refresh cycle of the fuse latch circuit, the latter is driven with pulses in such a way that the state of the fuse latch circuit is evaluated and only an incorrectly set fuse latch circuit is set to be correct.