Abstract: A system has an input and an output. The system includes a voltage converter, including first transistor coupled to the input and to a first switching node, second transistor coupled to the first switching node and to ground, third transistor coupled to a second switching node and to the output, fourth transistor coupled to the second switching node and to ground, and an inductor having a first terminal coupled to the first switching node and a second terminal coupled to the second switching node. The system also includes a controller coupled to the voltage converter, the controller including a state machine and a plurality of drivers to control the transistors of the voltage converter. The state machine is adaptable to cause the second and fourth transistors to conduct and the first and third transistors not to conduct, in response to current through the inductor being less than a current threshold.

Abstract: A system has an input and an output. The system includes a voltage converter, including first transistor coupled to the input and to a first switching node, second transistor coupled to the first switching node and to ground, third transistor coupled to a second switching node and to the output, fourth transistor coupled to the second switching node and to ground, and an inductor having a first terminal coupled to the first switching node and a second terminal coupled to the second switching node. The system also includes a controller coupled to the voltage converter, the controller including a state machine and a plurality of drivers to control the transistors of the voltage converter. The state machine is adaptable to cause the second and fourth transistors to conduct and the first and third transistors not to conduct, in response to current through the inductor being less than a current threshold.

Abstract: A buck-boost converter includes a voltage input terminal, a voltage output terminal, a first switch, a second switch, an inductor, a third switch, and an auxiliary capacitor. The first switch includes a first terminal coupled to the voltage input terminal, and a second terminal. The second switch includes a first terminal coupled to the voltage output terminal, and a second terminal. The inductor is coupled between the second terminal of the first switch and the second terminal of the second switch. The third switch includes a first terminal coupled to the second terminal of the second switch, and a second terminal. The auxiliary capacitor is coupled to the second terminal of the third switch.

Abstract: A controller includes a comparator having an inverting input coupled to a voltage converter output, a non-inverting input coupled to a voltage source, and an output. The controller includes a timer having a start input coupled to the converter that indicates that current through a converter inductor is less than a threshold; a stop input coupled to the comparator output; and an output having a digital value corresponding to the time between receiving asserted signals at start input and at stop input. The controller includes a time comparator having a first input coupled to the timer output and a second input to receive a time value. The time comparator asserts one of its outputs based on the digital and time values. The controller includes an accumulator coupled to the time comparator outputs, the accumulator configured to maintain, increase, or decrease an output value based on the asserted time comparator output.

Abstract: A system has an input and an output. The system includes a voltage converter, including first transistor coupled to the input and to a first switching node, second transistor coupled to the first switching node and to ground, third transistor coupled to a second switching node and to the output, fourth transistor coupled to the second switching node and to ground, and an inductor having a first terminal coupled to the first switching node and a second terminal coupled to the second switching node. The system also includes a controller coupled to the voltage converter, the controller including a state machine and a plurality of drivers to control the transistors of the voltage converter. The state machine is adaptable to cause the second and fourth transistors to conduct and the first and third transistors not to conduct, in response to current through the inductor being less than a current threshold.

Abstract: A controller includes a comparator having an inverting input coupled to a voltage converter output, a non-inverting input coupled to a voltage source, and an output. The controller includes a timer having a start input coupled to the converter that indicates that current through a converter inductor is less than a threshold; a stop input coupled to the comparator output; and an output having a digital value corresponding to the time between receiving asserted signals at start input and at stop input. The controller includes a time comparator having a first input coupled to the timer output and a second input to receive a time value. The time comparator asserts one of its outputs based on the digital and time values. The controller includes an accumulator coupled to the time comparator outputs, the accumulator configured to maintain, increase, or decrease an output value based on the asserted time comparator output.

Abstract: A method of capacitance-to-voltage conversion with an external sensor capacitor (CP) and a capacitance-to-voltage converter (14) implemented on an integrated readout circuit that includes a reference capacitor (CR), a sampling capacitor (CS) and a sampling amplifier (22) and which has input terminals (16) to which the sensor capacitor (CP) is connected. The method comprises the steps of a) applying a reference voltage (Vref) to the series connected sensor capacitor (CP) and reference capacitor (CR) and charging the sampling capacitor (CS) to the potential at the interconnection node (A) between the sensor capacitor (CP) and the reference capacitor (CR), b) connecting the sampling capacitor (CS) to inputs of the sampling amplifier.

Abstract: A transponder device comprises an integrated CMOS circuit with a semiconductor substrate. A first rectifying diode (DS) is formed by the substrate diode of the CMOS circuit. A first MOS transistor structure (DR1) and a second MOS transistor structure (DR2) have their channels connected in series such that they function as a second rectifying diode, the cathode of the first rectifying diode being connected to the anode of the second rectifying diode. The first MOS transistor structure (DR1) and the second MOS transistor structure (DR2) are spaced from each other such that a distance between the two MOS transistor structures is large enough that a parasitic npn-structure formed within the substrate by the first and the second MOS structures has a negligible current gain.

Abstract: A transponder device comprises an integrated CMOS circuit with a semiconductor substrate. A first rectifying diode (DS) is formed by the substrate diode of the CMOS circuit. A first MOS transistor structure (DR1) and a second MOS transistor structure (DR2) have their channels connected in series such that they function as a second rectifying diode, the cathode of the first rectifying diode being connected to the anode of the second rectifying diode. The first MOS transistor structure (DR1) and the second MOS transistor structure (DR2) are spaced from each other such that a distance between the two MOS transistor structures is large enough that a parasitic npn-structure formed within the substrate by the first and the second MOS structures has a negligible current gain.

Abstract: A method of capacitance-to-voltage conversion with an external sensor capacitor (CP) and a capacitance-to-voltage converter (14) implemented on an integrated readout circuit that includes a reference capacitor (CR), a sampling capacitor (CS) and a sampling amplifier (22) and which has input terminals (16) to which the sensor capacitor (CP) is connected. The method comprises the steps of a) applying a reference voltage (Vref) to the series connected sensor capacitor (CP) and reference capacitor (CR) and charging the sampling capacitor (CS) to the potential at the interconnection node (A) between the sensor capacitor (CP) and the reference capacitor (CR), b) connecting the sampling capacitor (CS) to inputs of the sampling amplifier.