Abstract: An apparatus is disclosed that includes a semiconductor device to control a power converter having two or more power FETs. The semiconductor device includes a gate signal generator configured to produce two or more gate signals able to drive the two or more FETs. The gate signal generator has programmable timing configuration parameters to control operation of the two or more gate signals, wherein the timing configuration parameters are digitally programmed via a memory in the semiconductor device. The memory may be implemented with fuses, other non-volatile memory or volatile memory. The parameters may be fixed or updated during a lifetime of the apparatus. A serial-to-parallel conversion may be used to input the parameters. Optimization methods may be performed to determine parameters considered to be optimal. The apparatus may also include the power converter.

Abstract: An apparatus is disclosed that includes a semiconductor device to control a power converter having two or more power FETs. The semiconductor device includes a gate signal generator configured to produce two or more gate signals able to drive the two or more FETs. The gate signal generator has programmable timing configuration parameters to control operation of the two or more gate signals, wherein the timing configuration parameters are digitally programmed via a memory in the semiconductor device. The memory may be implemented with fuses, other non-volatile memory or volatile memory. The parameters may be fixed or updated during a lifetime of the apparatus. A serial-to-parallel conversion may be used to input the parameters. Optimization methods may be performed to determine parameters considered to be optimal. The apparatus may also include the power converter.

Abstract: A method of incorporating noise considerations during circuit optimization includes the steps of: specifying a circuit schematic to be optimized; specifying at least one noise criterion as a noise measurement, including the signal to be checked for noise, the sub-interval of time of interest, and the maximum allowable noise deviation; providing each noise criterion as either a semi-infinite constraint or a semi-infinite objective function; specifying at least one variable of the optimization; converting the semi-infinite noise constraints and the semi-infinite noise objective functions into time-integral equality constraints; optionally, if required, providing additional optimization criteria other than noise as, for each such criterion, either objective functions or constraints; creating a merit function to be minimized to solve the optimization problem; simulating the circuit in the time-domain; computing the values of the objective functions and constraints; efficiently computing the gradients of the merit

Abstract: A high performance register that can be used as a pipelined register in logic chips that are designed using a pulsed logic methodology is described. The register features minimal setup time, pulse catching and pulse launching. The register circuitry complies with and implements a circuit-level test methodology for pulsed logic that features the ability to inhibit the reset of pulses, to force resets and to operate the circuits in a pseudo static mode. The register also complies with the level sensitive scan design (LSSD) methodology. Also described is a state-holding static master-slave register that complies with a pulsed logic design methodology, the register exhibiting an automatic power reduction feature and a simplified modular register bit design which can easily be adapted to either static domino or pulsed logic. The register is also LSSD compliant. Also described is the means and method for allowing static transmission gate input registers to comply with the static evaluate test mode.

Abstract: A method of efficient computation of gradients of a merit function of a system includes the steps of: specifying at least one parameter for which the gradients with respect to the at least one parameter are desired; specifying the merit function of interest in terms of observable measurements of the system; either solving or simulating the system to determine values of the measurements; expressing the gradients of the merit function as the gradient of a weighted sum of measurements; forming an appropriately configured adjoint system; and either solving or simulating the adjoint system to simultaneously determine the gradients of the merit function with respect to the at least one parameter by employing a single adjoint analysis.

Abstract: A pulsed logic circuit test methodology and circuitry therefor are disclosed. The methodology and circuitry allow the inhibiting of reset pulses, the ability to force resets and the ability to test the circuit in a pseudo-static mode of operation.