Patents by Inventor Rudolf Bitzinger

Rudolf Bitzinger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8797853
    Abstract: An access control function (ZF) which checks a requested use (NU) of a service (DI) by considering an available capacity Cv which is detected by considering the entire transmission capacity (G) and is available to an access node (ZK) for transmitting traffic flows (VS) to the communications network. The service is carried out in at least one communications network (KN) that is provided with an entire transmission capacity (G). The access node (ZK) is allocated to the access control function (ZF) which checks the requested use (NU) of the service (DI).
    Type: Grant
    Filed: March 7, 2001
    Date of Patent: August 5, 2014
    Assignee: Siemens Aktiengesellschaft
    Inventors: Rudolf Bitzinger, Christian Prehofer, Viktor Ransmayr
  • Publication number: 20090279450
    Abstract: For a service which is provided in at least one communications network preferably an Internet with service classes—which transmits packets and/or packet streams on a packet-oriented basis as a function of Qualities of Service, use of a service is requested with a controller, and this controller allocates a Quality of Service for the requested use as a function of the service and/or of the requested use of the service. A VoIP service implemented in accordance with International Standard H.323 can thus be used with a required Quality of Service.
    Type: Application
    Filed: November 7, 2008
    Publication date: November 12, 2009
    Applicant: Nokia Siemens Networks GmbH & Co. KG
    Inventors: Rudolf Bitzinger, Christian Prehofer, Viktor Ransmayr
  • Patent number: 7106737
    Abstract: A system and method for providing Quality of Service in an Ethernet network. One or more telephony application programs are provided, along with an H.323 Recommendation stack, an IP layer, and modular Generate QoSEthernet and QoSEthernet layers. The Generate QoSEthernet layer is adapted to read Type of Service or Differentiated Service bytes and generate desired QoSEthernet commands therefrom. Either the Generate QoSEthernet layer or the QoSEthernet layer may be replaced or modified without necessarily having to modify the H.323 Recommendation stack and application program(s).
    Type: Grant
    Filed: April 10, 2000
    Date of Patent: September 12, 2006
    Assignee: Siemens Communications, Inc.
    Inventors: William J. Beyda, Rudolf Bitzinger
  • Patent number: 6901080
    Abstract: A Generate QoSEthernet layer (118) is provided, interposed between an IP layer and a QoSEthernet layer (115). The Generate QoSEthernet layer (118) intercepts call commands, such as call setup commands, and identifies a required QoS for the particular call. The Generate QoSEthernet layer (118) then generates the QoS request commands required by the QoSEthernet layer (115).
    Type: Grant
    Filed: April 10, 2000
    Date of Patent: May 31, 2005
    Assignee: Siemens Communoications, Inc.
    Inventors: William J. Beyda, Rudolf Bitzinger
  • Publication number: 20030161267
    Abstract: The invention relates to an access control function (ZF) which checks a requested use (NU) of a service (DI) by considering an available capacity CV which is detected by considering the entire transmission capacity (G) and is available to an access node (ZK) for transmitting traffic flows (VS) to the communications network. Said service is carried out in at least one communications network (KN) that is provided with an entire transmission capacity (G). Said access node (ZK) is allocated to the access control function (ZF) which checks whether said requested use (NU) of the service (DI).
    Type: Application
    Filed: March 27, 2003
    Publication date: August 28, 2003
    Inventors: Rudolf Bitzinger, Christian Prehofer, Viktor Ransmayr
  • Patent number: 4914572
    Abstract: A method provides error protection in a multiprocessor central control unit of a switching system wherein a number of central processors (CP, IOC) as well as a central memory (CMY) are connected in parallel to a central bus system (B:CMY0/B:CMY1). The processors include dual highly-synchronous parallel driven processor units (PU) --apart from a possible tolerable positive timing slip--and integral error detection circuits (V), as well as an integral local memory (LMY), in the ROM-area of which test program sections are stored for testing the respective processors (CP, IOC). Upon the detection of an error by at least one of the error detection circuits (V) of a processor (for example CPx), in the respective processor (CPx), at least if the error is not immediately correctable, the error detection circuit (V in CPx) starts isolating the respective processor (CPx) from the bus system (B:CMY).
    Type: Grant
    Filed: March 11, 1987
    Date of Patent: April 3, 1990
    Assignee: Siemens Aktiengesellschaft
    Inventors: Rudolf Bitzinger, Walter Engl, Siegfried Humml, Klaus Schreier
  • Patent number: 4912698
    Abstract: A method and apparatus for operating a multiprocessor control computer provides that at least one part of the central processors may be connected through switches to each half of a duplicated central bus system and through switches to each half of duplicated memory banks of a common memory. With the duplication and selectable switching, the multiprocessor control computer may be normally operated while the remainder of the computer may be connected to a special computer for modification of the normal operating program. Data already in one memory bank can also be stored in another memory bank under the same address so that after the special operating time of both memory banks, the memory banks contain the same information at the same addresses. Two specific processors are provided for operating and security functions, while the remainder of the processors carry out exchange functions.
    Type: Grant
    Filed: June 13, 1988
    Date of Patent: March 27, 1990
    Assignee: Siemens Aktiengesellschaft
    Inventors: Rudolf Bitzinger, Walter Engl, Siegfried Humml, Klaus Schreier
  • Patent number: 4860333
    Abstract: A multiprocessor central control unit a switching system with a main memory (CMY) including, aside from a tolerable timing slip, synchronously parallel operated memory block pairs (MB3a/MB3b) during normal operation. The main memory (CMY), together with the central processors (BP, CP . . . IOC . . . ), is connected to a central bus system (B:CMY0/CMY1). The data stored in parallel in the memory blocks of the memory block pairs (e.g., MB3a/MB3b) are EDC-protected. The processors have access to the memory block pairs (e.g. MB3a/MB3b). Upon the occurrence of a multiple error in an indicated second memory block (e.g., MB3b) of a memory block pair (MB3a/MB3b), the second memory block (MB3b) is isolated from the bus system (B:CMY0/B:CMY1) via an automatic memory configuration.
    Type: Grant
    Filed: March 11, 1987
    Date of Patent: August 22, 1989
    Assignee: Oread Laboratories, Inc.
    Inventors: Rudolf Bitzinger, Walter Engl, Siegfried Humml, Klaus Schreier