Patents by Inventor Rudolf Buchta

Rudolf Buchta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5491112
    Abstract: A method for treating a silicon plate, a so-called wafer, in a cold-wall reactor when using the so-called CVD-technique in order, among other things, to deposit substances on the silicon plate by introducing different gases into the reactor. The reactor is configured as a microwave cavity, and one treatment stage involves introducing microwave energy into the reactor from a microwave generator, thereby to heat the silicon plate to a desired temperature, which is measured in a known manner. According to one preferred embodiment, a suitable etching gas is introduced into the cold-wall reactor, and microwave energy is then introduced into the reactor at a power level such as to form a plasma in the reactor, to thereby back-etch a substrate or to clean the reactor from possible impurities contained therein.
    Type: Grant
    Filed: November 19, 1993
    Date of Patent: February 13, 1996
    Assignee: Im Institutet For Mikroelektronik
    Inventors: Rudolf Buchta, Yngve Hassler
  • Patent number: 4740484
    Abstract: A method for manufacturing integrated circuits in which conductors and gate structures are built-up on a substrate plate, the conductors incorporating a layer of polycrystalline silicon and the gate structures including a gate electrode of polycrystalline silicon, where each of the gate structures is surrounded by doped source-and-drain-areas and where the gate electrode and the source-and-drain-areas respectively are metallized by depositing thereon a metal which reacts with the silicon from which the gate electrode and the source-and-drain-areas are comprised, so as to form a silicide layer. In accordance with the invention the gate electrode (3) is metallized in a first process stage. The source-and-drain-areas (18, 19) are metallized in a later process stage. Subsequent to metallizing the gate electrode in the first process stage, a protective layer (5) is applied to the metallized layer (4) of the gate electrode in a second process stage.
    Type: Grant
    Filed: October 30, 1986
    Date of Patent: April 26, 1988
    Assignee: Stiftelsen Institutet for Mikrovagsteknik VID Tekniska Hogskolan I Stockholm
    Inventors: Hans Norstrom, Sture Petersson, Rudolf Buchta