Abstract: Techniques are described for dynamically controlling the execution of operations within a multi-operation instruction, such as a very long instruction word (VLIW). A programmable processor fetches and executes a first instruction having an operation mask. Based on the operation mask, the processor selectively executes one or more operations within a second instruction. Individual operations within a multi-operation instruction can be selectively enabled and disabled, which is advantageous in many situations, including event handling and code debugging.

Abstract: The invention is directed to techniques for managing a cache within a processor using one or more machine instructions. The machine instructions may perform one or more operations on the cache. For example, victimize instructions, allocate instructions, and pre-fetch instructions can be executed in the processor as part of cache management. Moreover, these various cache management instructions may be defined by one or more operands that specify memory addresses within main memory, rather than addresses or identifiers that define locations within the cache. For this reason, a programmer may invoke these cache management instructions to direct the management of the cache without knowing the specific location of data within the cache.

Abstract: A communication bus system is disclosed. More particularly, the communication bus system includes requesting stations that can issue request packets via a bus and an execution station. The execution station receives the request packets and executes commands modifying the same aspect of a state of the execution station in response to request packets from different stations. The execution station keeps information concerning execution of commands which were last executed in response to request packets for all the different requesting stations. The requesting stations can read this information to determine whether the commands corresponding to their packets are executed, even when other requesting stations are also issuing request packets. Preferably, the execution station shows each requesting station only the information about the execution of commands executed to its own request packets.

Abstract: A data bus system comprises a number of stations which are interconnected via a bus. The bus has a limited data transmission capacity available. From a transmitter station a resource control station reads which part of the available transmission capacity is required for the relevant transmitter. The resource control station allocates the required transmission capacity to the relevant transmitter station if adequate transmission capacity is available; it is only in that case that transmission by the relevant transmitter station is enabled.

Abstract: A data bus system has a number of stations which are interconnected via a bus. The bus has a limited data transmission capacity available. From a transmitter station a resource control station reads which part of the available transmission capacity is required for the relevant transmitter. The resource control station allocates the required transmission capacity to the relevant transmitter station if adequate transmission capacity is available. Only if adequate transmission capacity is available is transmission by the relevant transmitter station enabled.

Abstract: A system associates a time-stamp with data inputted at its input, specifying an instant with a predetermined delay after receiving the data. The system outputs said data at an output according to the time-stamp. Inputting and outputting is timed by different clocks, which are periodically synchronized. At certain times the source of synchronization may change, potentially causing a discontinuity in synchronized time. The system contains potential discontinuity signalling means, for signalling a potential discontinuity in a progression of the clocked time. The predetermined relation is corrected when such a potential discontinuity is signalled for an instant between inputting and outputting the data.

Abstract: A signal processing system comprising a source apparatus coupled to a destination apparatus, the source apparatus being arranged for supplying the destination apparatus with a signal comprising video data, a time-stamp and synchronization data representing a time-value of an instant of said supplying, the destination apparatus being arranged for receiving the signal, synchronizing a time-value of a clock in accordance with the synchronization data, detecting when the time-value of the clock corresponds to the time-stamp and for thereupon presenting the video data at an output. The system includes a bus operable according to a time-slot allocation protocol, the source apparatus supplying the signal to the destination apparatus via the bus, the source apparatus including a first interface unit for buffering the signal until an allocated time-slot is available on the bus, the source apparatus setting the synchronization data according to an instant the signal is supplied to the first interface unit.

Abstract: A signal processing system contains a source apparatus coupled to a destination apparatus via a bus operable according to a time-slot allocation protocol. The source apparatus is arranged for supplying a sequence of packets, each having a time-stamp via the bus to the destination apparatus. The destination apparatus includes a clock and is arranged for receiving the packets, for detecting when the time-value of the clock corresponds to the time-stamp in a particular packet, and for thereupon presenting data from that particular packet at an output, operable according to a time-slot allocation protocol. The source apparatus is arranged for supplying a first and a second part of at least one of the packets in different time-slots, the destination apparatus being arranged for presenting data from the first and second part together upon detecting when the time-value of the clock corresponds to the time-stamp in the at least one of the packets.