Abstract: A non-switched, DC coupled vertical deflection circuit includes a source of a first DC supply voltage that is coupled to a first end terminal of a vertical deflection winding. An amplifier is energized by a second DC supply voltage having twice the magnitude of the first DC supply voltage and the same polarity. An output voltage of the amplifier having the same polarity of each of the first and second DC supply voltages is developed at a second end terminal of the deflection winding. The amplifier produces a deflection current at opposite polarities, during corresponding portions of a vertical trace interval.

Abstract: In a vertical sawtooth generator of a vertical deflection circuit, a first comparator generates an output signal when a retrace portion of a sawtooth signal is at a first magnitude to initiate a vertical trace portion of the sawtooth signal. An amplifier responsive to the sawtooth signal and to a reference signal generates a feedback current at a time that occurs between the center of vertical trace and the end of trace and away from the center of trace. The feedback current is determined in accordance with a difference between the sawtooth signal and the reference signal. The feedback current is coupled to a first capacitor to develop a gain control voltage. The control voltage is applied via a voltage-to-current converter to an integrating capacitor to develop in the integrating capacitor the trace portion of the sawtooth signal. The control voltage is initialized during a power start-up interval.

Abstract: In a vertical sawtooth generator of a vertical deflection circuit, a first comparator generates an output signal when a retrace portion of a sawtooth signal is at a first magnitude to initiate a vertical trace portion of the sawtooth signal. An amplifier responsive to the sawtooth signal generates a feedback current at a time that occurs between the center of vertical trace and the end of trace and away from each of the center and end of trace. The feedback current is coupled to a first capacitor to develop a control voltage. The control voltage is applied via a voltage-to-current converter to an integrating capacitor to develop in the integrating capacitor the trace portion of the sawtooth signal. The control voltage is initialized during a power start-up interval.

Abstract: An apparatus for generating an intermediate voltage having a value between a positive voltage supply value and a negative supply value. The apparatus has low power dissipation and is dynamically stable over a range of external supply voltages. The apparatus comprises a voltage comparator having first and second input terminals and a control signal output terminal. A reference voltage generator is coupled to the positive voltage supply and generates a reference voltage which is coupled to the first input terminal of the comparator. A device having a zener characteristic is coupled to the positive voltage supply and generates a voltage which is coupled to the second input terminal of the comparator. A current source is coupled to the negative voltage supply and generates a current which is coupled to a terminal, to form the intermediate voltage, and is also coupled to the device to determine the voltage generated thereby.

Abstract: For the purpose of a high precision frequency fine tuning, for example, to a certain television channel, an analog circuit, the frequency of which can be balanced, for example, an demodulator, is balanced in an integrated circuit with the help of a control current. The control current generated in a regulating loop is dependent on a reference frequency with the appropriate accuracy and on a reference frequency with the appropriate accuracy and on a reference capacitancy integrated on the chip. After selecting a frequency, the analog circuit is calibrated and the frequency is subsequently fine-tuned in a measuring mode. Following that, the analog circuit operates in the normal mode.

Abstract: An integrated control circuit forms a driver stage of an output transistor of a switch mode power supply. During a start-up interval of a run mode operation, the control circuit does not consume supply current and does not produce a switching control signal for switching the transistor. During an initialization interval that follows the start-up interval, a reference voltage source that is included in the control circuit is turned on and internal conditions in the control circuit are defined. The switching control signal is generated following the initialization interval.

Abstract: The relationship of a reference current of a current balancing circuit to a first output current at the collector of an output transistor is adjusted via the dimensioning of a first resistance R in the emitter of the output transistor of a current balancing circuit. By adding a second current balancing circuit with a second resistor R' contained therein and which provides a second output current, there results, for R=R', the relationship of the first output current to the second output current corresponding to the relationship of the reference current to the first output current.

Abstract: A frequency compensated circuit includes a frequency compensation component and a negative feedback loop for feeding an output signal to the circuit input terminal. The circuit input terminal also receives a compensation signal from the frequency compensation component. A controlled system provides an output signal to the input terminal. A controlled current is supplied to the controlled system to increase the output voltage and the compensation signal from the compensation component can be substantially lower than it is in the prior art type of systems.

Abstract: A method of controlling the switching transistor in the switch mode power supply of a television receiver includes the steps of selectively operating the transistor in a stand-by state, a start-up state and an ON-state. During the stand-by state the switching transistor is rendered conductive by applying bursts of pulses at a frequency above, and unsynchronized with, the line frequency of the television receiver. The pulses are separated by changing intervals. During the start-up state the frequency of said bursts of the pulses is continuously reduced and pulses and the duration of the on time of the transistor is determined using a regulation voltage. During the ON-state, line synchronizing pulses are applied and the switching transistor is regulated to the line frequency.

Abstract: A phase control circuit for controlling the relative phase of periodic components of two logic signals having the same frequency, and one of which periodic components has a pulse-duty factor different from 50:50, said circuit includes a signal source which provides a control signal for regulating the relative phase of the periodic components of said logic signals. The control signal has a first value for phase relationships in a predetermined range of values and a second value for phase relationships outside said range of values. A phase lock detector detects the lock status of the periodic components of the logic signals. Another signal source provides a third logic signal having a periodic component having the same frequency as the periodic component of each of the two logic signals and a pulse width substantially wider than that of the two logic signals.

Abstract: A circuit for generating a vertical frequency deflection current for the electron beams in the picture tube of a television receiver includes a current sensor resistor having one end connected to direct voltage potential by two resistors connected in series and a second end connected to a vertical frequency sawtooth signal by two additional resistors connected in series. An error signal generator has one input terminal connected to the junction the first two resistors and another input terminal connected the junction of the second two resistors. An output stage supplies the deflection current. The output terminal of the error signal generator is connected to the input terminal of the output stage. The error amplifier is a transconductance amplifier having an output terminal connected to reference potential by a series connection of a resistor and a capacitor.

Abstract: A scanning circuit which utilizes blanking pulses between flyback pulses in a display device includes a line blanking circuit which prevents the generation of spurious blanking pulses by ringing in the blanking pulses. The line blanking circuit includes a capacitor for storing a reference voltage. A comparator is responsive to the reference voltage and to the flyback pulses and provides the blanking pulses when the flyback pulses exceed the reference voltage. The comparator is prevented from resetting for a preselected time period after the falling edge of the blanking pulse and spurious blanking pulses can not be generated during the preselected time period.

Abstract: A circuit for detecting a square wave television signal in a television receiver includes an oscillator for generating the square wave signal and a phase locked loop (PLL) for synchronizing the square wave signal with the syn pulses of the televsion receiver. The circuit also includes an integrator for switching the output signal of the PLL to a frequency stable square wave signal when the syn pulses are absent and a Schmitt trigger for closing the PPL when a threshold value is reached. With the invention, the syn signals are sensed and a first switchable constant current source increases the output voltage of the integrator for a predetermined period of time when syn pulses are present during the first half of the square wave signal and discharges the integrator when syn signals are absent from the second half of the square wave signal.