Patents by Inventor Rudolf Schlangen

Rudolf Schlangen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160202126
    Abstract: A method for localizing a hot spot (27) in a sample (12), in particular an encapsulated device under test (DUT), by using lock-in thermography (LIT), where at least one heat source (23) of an electrical circuit is buried within the sample (12) and generated the hot spot (27) upon flow of current therein, comprises applying a non-harmonic excitation wave test signal at a lock-in frequency to the electrical circuit of the sample (12) to activate the heat source (23) for generating the hot spot (27); imaging the sample (12) using an infrared sensor (16) to obtain IR images of the sample (12) while the non-harmonic test signal is applied to the electrical circuit; and detecting a thermal response signal obtained from the imaging, the thermal response signal being in correlation to the thermal heat propagation within the sample (12).
    Type: Application
    Filed: May 30, 2014
    Publication date: July 14, 2016
    Inventors: Christian Schmidt, Raiko Meinhardt-Wildegger, Frank Altmann, Falk Naumann, Rudolf Schlangen
  • Patent number: 9322715
    Abstract: A non-destructive approach for the 3D localization of buried hot spots in electronic device architectures by use of Lock-in Thermography (LIT). The 3D analysis is based on the principles of thermal wave propagation through different material layers and the resulting phase shift/thermal time delay. With more complex multi level stacked die architectures it is necessary to acquire multiple LIT results at different excitation frequencies for precise hot spot depth localization. Additionally, the use of multiple time-resolved thermal waveforms, measured in a minimized field of view on top of the hot spot location, can be used to speed up the data acquisition. The shape of the resulting waveforms can be analyzed to further increase the detection accuracy and confidence level.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: April 26, 2016
    Assignees: DCG SYSTEMS, INC., FRAUNHOFER-GESELLSCHAFT ZUR FĂ–RDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
    Inventors: Frank Altmann, Christian Schmidt, Rudolf Schlangen, Herve Deslandes
  • Publication number: 20150338458
    Abstract: Controlled amount of heat is injected into a stacked die using a light beam, and the propagated heat is measuring with LIT camera from the other side of the die. The thermal image obtained can be characterized so that it can be used to calibrate the phase shift from a given stack layer, or can be used to identify defects in the stacked die. The process can be repeated for each die in the stack to generate a reference for future testing. The thermal image can be investigated to detect faults, such as voids in vias, e.g., TSV.
    Type: Application
    Filed: August 3, 2015
    Publication date: November 26, 2015
    Inventors: Herve Deslandes, Rudolf Schlangen, Prasad Sabbineni, Antoine Reverdy, Ingrid De Wolf
  • Patent number: 9098892
    Abstract: Controlled amount of heat is injected into a stacked die using a light beam, and the propagated heat is measuring with LIT camera from the other side of the die. The thermal image obtained can be characterized so that it can be used to calibrate the phase shift from a given stack layer, or can be used to identify defects in the stacked die. The process can be repeated for each die in the stack to generate a reference for future testing. The thermal image can be investigated to detect faults, such as voids in vias, e.g., TSV.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: August 4, 2015
    Assignee: DCG SYSTEMS, INC.
    Inventors: Herve Deslandes, Rudolf Schlangen, Prasad Sabbineni, Antoine Reverdy, Ingrid De Wolf
  • Patent number: 9025020
    Abstract: Controlled amount of heat is injected into a stacked die using a light beam, and the propagated heat is measuring with LIT camera from the other side of the die. The thermal image obtained can be characterized so that it can be used to calibrate the phase shift from a given stack layer, or can be used to identify defects in the stacked die. The process can be repeated for each die in the stack to generate a reference for future testing. The thermal image can be investigated to detect faults, such as voids in vias, e.g., TSV.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: May 5, 2015
    Assignee: DCG Systems, Inc.
    Inventors: Herve Deslandes, Rudolf Schlangen, Prasad Sabbineni, Antoine Reverdy, Ingrid De Wolf
  • Publication number: 20140346360
    Abstract: A non-destructive approach for the 3D localization of buried hot spots in electronic device architectures by use of Lock-in Thermography (LIT). The 3D analysis is based on the principles of thermal wave propagation through different material layers and the resulting phase shift/thermal time delay. With more complex multi level stacked die architectures it is necessary to acquire multiple LIT results at different excitation frequencies for precise hot spot depth localization. Additionally, the use of multiple time-resolved thermal waveforms, measured in a minimized field of view on top of the hot spot location, can be used to speed up the data acquisition. The shape of the resulting waveforms can be analyzed to further increase the detection accuracy and confidence level.
    Type: Application
    Filed: June 2, 2014
    Publication date: November 27, 2014
    Applicants: DCG Systems, Inc., Fraunhofer-Gesellschaft zur Forderung der angewandten Forschung e.V.
    Inventors: Frank Altmann, Christian Schmidt, Rudolf Schlangen, Herve Deslandes
  • Publication number: 20140210994
    Abstract: Controlled amount of heat is injected into a stacked die using a light beam, and the propagated heat is measuring with LIT camera from the other side of the die. The thermal image obtained can be characterized so that it can be used to calibrate the phase shift from a given stack layer, or can be used to identify defects in the stacked die. The process can be repeated for each die in the stack to generate a reference for future testing. The thermal image can be investigated to detect faults, such as voids in vias, e.g., TSV.
    Type: Application
    Filed: April 2, 2014
    Publication date: July 31, 2014
    Applicant: DCG Systems, Inc.
    Inventors: Herve Deslandes, Rudolf Schlangen, Prasad Sabbineni, Antoine Reverdy, Ingrid De Wolf
  • Patent number: 8742347
    Abstract: A non-destructive approach for the 3D localization of buried hot spots in electronic device architectures by use of Lock-in Thermography (LIT). The 3D analysis is based on the principles of thermal wave propagation through different material layers and the resulting phase shift/thermal time delay. With more complex multi level stacked die architectures it is necessary to acquire multiple LIT results at different excitation frequencies for precise hot spot depth localization. Additionally, the use of multiple time-resolved thermal waveforms, measured in a minimized field of view on top of the hot spot location, can be used to speed up the data acquisition. The shape of the resulting waveforms can be analyzed to further increase the detection accuracy and confidence level.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: June 3, 2014
    Assignees: DCG Systems, Inc., Fraunhofer-Gesellschaft zur Förderung der Angewandten Forschung e.V.
    Inventors: Frank Altmann, Christian Schmidt, Rudolf Schlangen, Herve Deslandes
  • Publication number: 20120098957
    Abstract: Controlled amount of heat is injected into a stacked die using a light beam, and the propagated heat is measuring with LIT camera from the other side of the die. The thermal image obtained can be characterized so that it can be used to calibrate the phase shift from a given stack layer, or can be used to identify defects in the stacked die. The process can be repeated for each die in the stack to generate a reference for future testing. The thermal image can be investigated to detect faults, such as voids in vias, e.g., TSV.
    Type: Application
    Filed: October 24, 2011
    Publication date: April 26, 2012
    Applicant: DCG SYSTEMS, INC.
    Inventors: Herve DESLANDES, Rudolf SCHLANGEN, Prasad SABBINENI, Antoine REVERDY
  • Publication number: 20110297829
    Abstract: A non-destructive approach for the 3D localization of buried hot spots in electronic device architectures by use of Lock-in Thermography (LIT). The 3D analysis is based on the principles of thermal wave propagation through different material layers and the resulting phase shift/thermal time delay. With more complex multi level stacked die architectures it is necessary to acquire multiple LIT results at different excitation frequencies for precise hot spot depth localization. Additionally, the use of multiple time-resolved thermal waveforms, measured in a minimized field of view on top of the hot spot location, can be used to speed up the data acquisition. The shape of the resulting waveforms can be analyzed to further increase the detection accuracy and confidence level.
    Type: Application
    Filed: June 8, 2011
    Publication date: December 8, 2011
    Inventors: Frank ALTMANN, Christian Schmidt, Rudolf Schlangen, Herve Deslandes
  • Publication number: 20080090403
    Abstract: An apparatus and method for forming a contact to silicide through an active diffusion region, a contact to a contact through an active diffusion region, and a contact to a polysilicon structure through a shallow trench isolation region to create a conductive connection with a circuit node of interest. In one embodiment, an opening through the active diffusion region to an associated silicide layer is used to form the conductive connection. In another embodiment, an opening through the active diffusion region to an associated contact is used to form the conductive connection. In yet another embodiment, an opening through a shallow trench isolation region to a polysilicon structure is used to form the conductive connection.
    Type: Application
    Filed: October 2, 2006
    Publication date: April 17, 2008
    Applicant: Credence Systems Corporation
    Inventors: Rudolf Schlangen, Uwe Jurgen Kerst, Peter Sadewater, Mark A. Thompson