Abstract: An explanation is given of an integrated interconnect arrangement having a plurality of interconnects that cross over one another at two crossover sections. By virtue of this measure, it is possible to achieve a uniform current flow in all three interconnects even at very high frequencies.

Abstract: A field-effect transistor (FET) structure and method of formation thereof is presented. The FET structure includes first and second source/drain regions formed in a semiconductor substrate to define a channel region. A gate insulation layer is formed at a surface of the channel region. A control layer is formed at a surface of the gate insulation layer. A diode doping region is formed to realize a diode in the semiconductor substrate. An electrically conductive diode connection layer connects the diode doping region to the control layer. A depression is formed in the semiconductor substrate. The diode doping region is formed at a bottom of the depression and the diode connection layer is formed in the depression to dissipate excess charge carriers in the semiconductor substrate.

Abstract: Integrated interconnect arrangement An explanation is given of an integrated interconnect arrangement (12) having a plurality of interconnects (LB1 to LB3) that cross over one another at two crossover sections (20, 24). By virtue of this measure, it is possible to achieve a uniform current flow in all three interconnects even at very high frequencies.

Abstract: The present invention provides a method for fabricating a semiconductor structure having a plurality of gate stacks (GS1, GS2, GS3, GS4) on a semiconductor substrate (10), having the following steps: application of the gate stacks (GS1, GS2, GS3, GS4) to a gate dielectric (11) above the semiconductor substrate (10); formation of a sidewall oxide (17) on sidewalls of the gate stacks (GS1, GS2, GS3, GS4); application and patterning of a mask (12) on the semiconductor structure; and implantation of a contact doping (13) in a self-aligned manner with respect to the sidewall oxide (17) of the gate stacks (GS1, GS2) in regions not covered by the mask (12).

Abstract: A field-effect transistor (FET) structure and method of formation thereof is presented. The FET structure includes first and second source/drain regions formed in a semiconductor substrate to define a channel region. A gate insulation layer is formed at a surface of the channel region. A control layer is formed at a surface of the gate insulation layer. A diode doping region is formed to realize a diode in the semiconductor substrate. An electrically conductive diode connection layer connects the diode doping region to the control layer. A depression is formed in the semiconductor substrate. The diode doping region is formed at a bottom of the depression and the diode connection layer is formed in the depression to dissipate excess charge carriers in the semiconductor substrate.

Abstract: The invention relates to a DRAM memory cell having a trench filled with conductive material connected to a selection transistor by a connection having a vertical insulation collar arranged perpendicularly to a layer sequence of the memory cell. The vertical insulation collar is connected to a lateral insulation collar of the trench. This lateral insulation collar essentially extends perpendicular to the vertical insulation collar or is arranged laterally with respect to the vertical insulation collar. It is thus possible to provide a memory cell, a wafer and a semiconductor component that have a high integration density and a sufficient dielectric strength, and that efficiently suppress parasitic transistors. A method for fabricating a lateral insulating collar for a memory cell is also described.

Abstract: A trench capacitor is formed in a trench, which is disposed in a substrate. The trench is filled with a conductive trench filling which functions as an inner capacitor electrode. An epitaxial layer is grown on the sidewall of the trench on the substrate. A buried strap is disposed between the conductive trench filling with the second intermediate layer and the epitaxially grown layer. A dopant outdiffusion formed from the buried strap is disposed in the epitaxially grown layer. Through the epitaxially grown layer, the dopant outdiffusion is further removed from a selection transistor disposed beside the trench, as a result of which it is possible to avoid short-channel effects in the selection transistor.

Abstract: A trench capacitor is formed in a trench, which is disposed in a substrate. The trench is filled with a conductive trench filling which functions as an inner capacitor electrode. An epitaxial layer is grown on the sidewall of the trench on the substrate. A buried strap is disposed between the conductive trench filling with the second intermediate layer and the epitaxially grown layer. A dopant outdiffusion formed from the buried strap is disposed in the epitaxially grown layer. Through the epitaxially grown layer, the dopant outdiffusion is further removed from a selection transistor disposed beside the trench, as a result of which it is possible to avoid short-channel effects in the selection transistor.

Abstract: The present invention provides a method for fabricating a semiconductor structure having a plurality of gate stacks (GS1, GS2, GS3, GS4) on a semiconductor substrate (10), having the following steps: application of the gate stacks (GS1, GS2, GS3, GS4) to a gate dielectric (11) above the semiconductor substrate (10); formation of a sidewall oxide (17) on sidewalls of the gate stacks (GS1, GS2, GS3, GS4); application and patterning of a mask (12) on the semiconductor structure; and implantation of a contact doping (13) in a self-aligned manner with respect to the sidewall oxide (17) of the gate stacks (GS1, GS2) in regions not covered by the mask (12).

Abstract: The invention relates to a DRAM memory cell having a trench filled with conductive material connected to a selection transistor by a connection having a vertical insulation collar arranged perpendicularly to a layer sequence of the memory cell. The vertical insulation collar is connected to a lateral insulation collar of the trench. This lateral insulation collar essentially extends perpendicular to the vertical insulation collar or is arranged laterally with respect to the vertical insulation collar. It is thus possible to provide a memory cell, a wafer and a semiconductor component that have a high integration density and a sufficient dielectric strength, and that efficiently suppress parasitic transistors. A method for fabricating a lateral insulating collar for a memory cell is also described.

Abstract: The use of hitherto known supported catalysts in chlorination processes and oxychlorination processes leads to high pressure drops and to the formation of hot spot temperatures in the reactor. When honeycomb monolithic catalyst supports provided with a multiplicity of channels open at both ends and parallel to the longitudinal axis are used, both the heat dissipation is improved and the pressure drops across the reactor are lowered drastically. This leads ultimately to an increase in the selectivity of the reaction and to a minimization of the combustion rate.

Abstract: In a process for the purification of hydrogen chloride from the pyrolysis of 1,2-dichloroethane, optionally after a preceding step of acetylene removal by selective hydrogenation under specific conditions followed by rectification of the resulting mixture to obtain hydrogen chloride containing at most 5 ppm of unsaturated hydrocarbons and at most 5 ppm of chlorinated hydrocarbons.

Abstract: In a method of treating the reaction product of pyrolysis of 1,2-dichloroethane to form vinyl chloride and hydrogen chloride with multiple stage cooling and distillation separation of the reaction product and recycle of unreacted 1,2-dichloroethane to the pyrolysis step, the improvement comprising direct cooling of the reaction product immediately after leaving the pyrolysis step, within 1 sec from a temperature range of 480.degree. to 540.degree. C. down to 150.degree. to 250.degree. C.

Abstract: An improved method of producing vinyl chloride by pyrolysis of purified 1,2-dichloroethane at temperatures from 480.degree. C. to 540.degree. C. at a pressure of 10 to 36 bar absolute with partial utilization of the heat content of the flue gases from the pyrolysis furnace firing to preheat liquid 1,2-dichloroethane almost to its boiling temperature utilizing the flue gas waste heat to generate steam, cool the pyrolysis gas mixture in several stages and separate the hydrogen chloride from the pyrolysis gas mix in a hydrogen chloride column as well as separate vinyl chloride from the pyrolysis gas mix in a vinyl chloride monomer column.

Abstract: In a process for preparation of 1,2-dichloroethane by chlorination of ethylene-containing reaction vent gases from the oxychlorination of ethylene in the presence of a catalyst carrier impregnated with metal compounds wherein the waste from the oxychlorination stage are chlorinated, the improvement comprising preheating the ethylene-containing waste gases to at least 50.degree. C. and then chlorinating the ethylene at 100.degree. to 300.degree. C. at a pressure of 1 to 7 bar with a space velocity of 100 to 5000 h.sup.-1 related to standard conditions in the presence of at least one metal compound selected from the group consisting of chlorides and oxides of manganese, nickel and cobalt supported on a catalyst carrier with reduced formation of oxychlorinated by-products.

Abstract: An improved process for the preparation of vinyl chloride from 1,2-dichloroethane (EDC) wherein 0.10 to 0.15 % by weight of carbon tetrachloride based on EDC, is used as a cracking promoter and the CHCl.sub.3 content is limited to less than 200 ppm. Before being fed to the cracking zone, the EDC is brought almost to the boiling point at 15 to 31 bar and then expanded to 10 to 16 bar with flashing EDC vapors and the fraction which has remained liquid is vaporized externally, and the combined EDC gas streams are heated, after being fed into the cracking furnaces, so that the energy required for cracking is already supplied in the first 75 to 85% of the reaction zone, whereby a conversion of 60 to 70% is obtained at residence time from 10 to 25 seconds and the exit temperature from the reaction zone is 485.degree. to 510.degree. C.

Abstract: A process of upgrading hydrogen chloride which contains chlorine, iron-III-chloride, acetylene and/or ethylene, for use in an oxichlorination process, wherein water in a gaseous state is added to the hydrogen chloride at temperatures between 120.degree. and 180.degree. C. within a time period of maximally 0.9 seconds after the acetylene and/or ethylene is present in the hydrogen chloride, together with chlorine and iron-III-chloride.

Abstract: A process for the work-up of chlorination residues by dissolving the same at temperatures between 100.degree. and 180.degree. C. in chlorine- and oxygen-containing hydrocarbons having a ratio by weight of hydrogen to chlorine of 0.028-0.06:1, a ratio by weight of oxygen:carbon of 0.0038-0.0089:1, and an atomic ratio of carbon:hydrogen of 1:1.1-1.9 and/or in hydrocarbons, boiling between 160.degree. and 380.degree. C. at one bar abs. and having an atomic ratio carbon:hydrogen of 1:1.85-2.0 so as to obtain a liquid preparation having a ratio by weight of hydrogen:chlorine of 0.028-0.05:1.

Abstract: A method for preparing hydrogen chloride resulting from chlorination reactions for use in the ethyleneoxichlorination process by reacting the chlorine contained in the hydrogen chloride with ethylene in the gaseous phase in the presence of carrier catalysts based on an iron-free transition metal chloride having an activity profile which increases in the flow direction, while maintaining the space-flow rates relatively high and the residence time of the gas in the reactor short. After discharge of the reaction product from the reactor the product is subjected to partial condensation advantageously performed in several steps.

Abstract: An improved process for the removal of acetylene from a hydrogen chloride stream in which the acetylene is converted to vinyl chloride by contact with a hydrochlorination catalyst, the improvement comprising, prior to contacting the stream with the hydrochlorination catalyst, contacting said stream with a catalyst comprising a noble metal, preferably of the platinum group, or salt or oxide thereof, supported or unsupported, at a temperature of between about 50.degree. and about 200.degree. C. and a pressure between about 8 and about 20 bar absolute.