Abstract: Wireless transceiver apparatus for operating in a part of the RF spectrum which is shared with a co-located second wireless transceiver apparatus. The first wireless transceiver apparatus includes, a wireless transceiver unit; an arbitration interface for interfacing with an arbitration entity which arbitrates access to the shared part of the RF spectrum between the first wireless transceiver apparatus and the second wireless transceiver apparatus; wherein the arbitration interface is adapted to signal time periods when the wireless transceiver unit is operational, or requests to be operational; and wherein the arbitration interface is adapted to signal data about and commands to the arbitration entity during other time periods. An enhanced arbitration entity is adapted to automatically detect and switch between two modes of interference reduction, e.g. a first interference reduction means such as AFR, a second interference reduction means such as PTA.

Abstract: A memory system for use with a master-slave type bus such as an AHB bus has a memory, a bus interface to allow memory access from the bus, and a direct memory access interface to allow memory access from a DMA controller without occupying the bus. The system can reduce occupancy of the bus, it can allow dedicated DMA access protocols faster than the bus protocol to be used, and can remove or reduce the need for bus arbitration and associated circuitry and delays. An arbiter can arbitrate between the memory accesses and give priority to DMA accesses.

Abstract: A code patching device is provided for use with a processor having a read-only memory which stores instruction code and a further memory for storing patch code. A plurality of patch address registers each store an address, in the read-only memory, at which a patch is to be performed. A comparator compares the address of the read-only memory that is being accessed by the processor with the addresses stored in the registers. A control unit selects between code from the read-only memory or patch code from the further memory depending on the comparison. The code patching device can replace, on-the-fly, erroneous lines of code from the read-only memory by corrected ones. During an initialization process the patch code is loaded into the further memory and the registers are loaded with the addresses which require patching.

Abstract: A memory system for use with a master-slave type bus such as an AHB bus has a memory, a bus interface to allow memory access from the bus, and a direct memory access interface to allow memory access from a DMA controller without occupying the bus. The system can reduce occupancy of the bus, it can allow dedicated DMA access protocols faster than the bus protocol to be used, and can remove or reduce the need for bus arbitration and associated circuitry and delays. An arbiter can arbitrate between the memory accesses and give priority to DMA accesses.

Abstract: Wireless transceiver apparatus for operating in a part of the RF spectrum which is shared with a co-located second wireless transceiver apparatus. The first wireless transceiver apparatus includes, a wireless transceiver unit; an arbitration interface for interfacing with an arbitration entity which arbitrates access to the shared part of the RF spectrum between the first wireless transceiver apparatus and the second wireless transceiver apparatus; wherein the arbitration interface is adapted to signal time periods when the wireless transceiver unit is operational, or requests to be operational; and wherein the arbitration interface is adapted to signal data about and commands to the first wireless transceiver apparatus during other time periods. An enhanced arbitration entity is adapted to automatically detect and switch between two modes or interference reduction, e.g. a first interference reduction means such as AFH, a second interference reduction means such as PTA.

Abstract: A memory system for use with a master-slave type bus such as an AHB bus has a memory, a bus interface to allow memory access from the bus, and a direct memory access interface to allow memory access from a DMA controller without occupying the bus. The system can reduce occupancy of the bus, it can allow dedicated DMA access protocols faster than the bus protocol to be used, and can remove or reduce the need for bus arbitration and associated circuitry and delays. An arbiter can arbitrate between the memory accesses and give priority to DMA accesses.

Abstract: A code patching device is provided for use with a processor having a read-only memory which stores instruction code and a further memory for storing patch code. A plurality of patch address registers each store an address, in the read-only memory, at which a patch is to be performed. A comparator compares the address of the read-only memory that is being accessed by the processor with the addresses stored in the registers. A control unit selects between code from the read-only memory or patch code from the further memory depending on the comparison. The code patching device can replace, on-the-fly, erroneous lines of code from the read-only memory by corrected ones. During an initialization process the patch code is loaded into the further memory and the registers are loaded with the addresses which require patching.