Abstract: A repeater provides an efficient interconnection of an IEEE 802.3 10 Mb/s network with an IEEE 802.3 100 Mb/s network using minimal buffering. The repeater includes a filter that selectively outputs a data packet, received from the 100 Mb/s network, to the 10 Mb/s network based on the destination address in the received data packet. Specifically, the filter passes all data packets in the 10 Mb/s domain to the 100 Mb/s domain. The filter selectively passes the data packet from the 100 Mb/s domain to the 10 Mb/s domain by determining if the received data packet includes a destination address value that specifies transmission of the data packet to the 10 Mb/s network. If the destination address value does not specify a multicast value or an address of a network node in the 10 Mb/s network, the filter discards the data packet.

Abstract: A serial display drive for an electronic system including control circuitry that manipulates a serial clock signal that synchronizes each of a plurality of status bits in a serial data stream. The serial display drive circuitry includes a set of indicating elements for displaying the status information and means for switching the indicating elements. The control circuitry periodically stops the serial clock signal to provide a status update interval for each of the indicating elements and to obviate the need for a register element and strobe signal to hold data for the light-emitting elements. In another embodiment, the control circuitry generates bar graph displays.

Abstract: There is disclosed herein a servo data decoder which can decode both quadrature and non quadrature servo data. The decoder is comprised of a servo data amplitude demodulator to generate position error signals and a position error signal processor to generate a GPES signal to serve as a position error signal during the track following mode and a velocity signal and a track crossing signal for use in the seek mode. The user system may have either single or double pulse sync, and double pulse sync spacing, pulse window time and sync to first data pulse delay are user definable. The user may adjust the gain of the system in two manners and may program the frequency response characteristics of the phase locked loop. Many other user definable or user alterable features are provided.

Abstract: There is disclosed herein an apparatus and method for generating a first signal related to the rate of change of a second signal. In particular, a system is disclosed for generating a velocity signal in a sampled data servo system. The apparatus uses three track and hold amplifiers one of which is also a difference amplifier to sample the position error signal at selected times. A "present" track and hold amplifier samples and holds the position error signal during the current frame. After this is done, during the same frame, a "summing" track and hold amplifier having its difference inputs coupled to the outputs of the "present" track and hold amplifier and to a "previous" track and hold amplifier samples the difference between the present position error signal and the value of the position error signal during the previous sample frame. This difference divided by the sample period gives the velocity.

Abstract: There is disclosed herein a servo data demodulator for use in magnetic head positioning servo system for disk drives. The demodulator is comprised of a single peak detector which detects the maximum amplitude of the peaks in an input signal during specific times. A storage capacitor is used in the peak detector to store the peak level. This peak level is sampled a predetermined number of times during each data frame. Each sample is taken by a different sample and hold circuit, and the sequence of the samples is controlled by a timing generator. The capacitor of the peak detector is discharged by a switch controlled by the timing generator after each sample and before the next sample. The time delay before the first sample from the start of the frame and the sample time in the sequence is programmable by the user by setting certain inputs into the timing generator.