Abstract: The history table of the present invention is utilized to record a context oriented predictor associated with one or more branch instructions. The context oriented predictor preferably is derived from the history table by incorporating within each entry of the history table a vector of branch predictors. This vector comprises for each value of n (where n can be arbitrarily set, yet preferably remains fixed within a given implementation), a set of 2 predictors. When the prefetching action of a processor causes the history table to be accessed, the vector of predictors for a given branch, called the ancestor branch, is retrieved from the history table and stored. After n such retrievals, the action history of the last n branches is used to access a predictor from the vector of predictors that was associated with the n-th ancestor (or predecessor) of the next upcoming branch. This predictor is used to predict the n-th successor branch of the ancestor branch.

Abstract: An apparatus and method for self-parallelizing and executing a sequence of instructions. During a first mode of operation, instructions are executed concurrently with the parallelizing of instructions sequences not already parallelized. During a second mode of operation, instruction sequences already parallelized during the first mode are executed in parallel asynchronously by separate processors. The separate processors share a common register file. The processing elements rename the registers used by the instructions that modify registers so when instructions are executed in parallel the result of the executions appear in the common set of registers accessible to all the processing elements. There is no need to send and receive obligation to resolve register set/use requirements implied by the sequential execution sequence.

Abstract: An improved cache coherency protocol is set forth that assures that a collection of processors in a multi-cache system configuration do not disagree about the precedence ordering of store operations that can originate from any and all processors within the system. The protocol maintains coherency while allowing lines to be modified by one processor while other processors access a prior unmodified copy of the line. The benefit of such a system is that line modification need not be done only for lines that are exclusive within the cache that is associated with the modifying processor. The manner in which this coherency is achieved is through the use of line status register which maintains the status of every line in the system and a processor modification register which maintains the identity of all processors that have been granted permission to modify a line that is shared with other processors.