Abstract: An apparatus to pre-condition an operating integrated circuit (IC) device in a static low power retention state. The apparatus includes a pseudo random number generator that generates a pseudo random number value to pre-condition the static low power retention state of the operating IC device. The apparatus also includes a controller that drives the pseudo random number value into a test scan chain linking logic elements of the operating IC device responsive to the operating IC device entering a sleep mode. Driving the pseudo random number value into the test scan chain by the controller places the operating IC device into the static low power retention state.

Abstract: An apparatus to pre-condition an operating integrated circuit (IC) device in a static low power retention state. The apparatus includes a pseudo random number generator that generates a pseudo random number value to pre-condition the static low power retention state of the operating IC device. The apparatus also includes a controller that drives the pseudo random number value into a test scan chain linking logic elements of the operating IC device responsive to the operating IC device entering a sleep mode. Driving the pseudo random number value into the test scan chain by the controller places the operating IC device into the static low power retention state.

Abstract: An integrated circuit is disclosed including one or more communication devices, an operational controller configured by a state device in a normal mode for the communication device, which may consume more power than in a low power mode. The operational controller retains an operational state in a normal mode for the communication device that may be corrupted during low power mode. A save-restore processor operates a configuration bus and an essentially non-volatile memory at the start a low power mode to retain the operational state and end of the low power mode to restore the operational state.

Abstract: An apparatus is disclosed that may include an integrated circuit (IC) with an initialization bus configured to communicate with at least one low power mode latch operating during a initialization mode to set a value into the low power mode latch and configured to respond to the assertion of a low power mode signal by selecting the low power mode latch state to drive at least one logic gate to minimize leakage current during the low power mode. The IC may similarly configure and operate a RAM. A leakage control table may be used during initialization mode and created by other embodiments. The net list of a circuit block including at least part of the configuration block and lower power control latch may be used and/or modified to create a new net list to further minimize leakage current during low power mode. Installation packages and program systems are disclosed.