Abstract: A power supply is configured to perform an at least partial compensation of a voltage variation caused by a load change using a voltage variation compensation mechanism which is triggered in response to an expected load change. An Automated test equipment for testing a device under test comprises a power supply, which is configured to supply the device under test. The automated test equipment comprises a pattern generator configured to provide one or more stimulus signals for the device under test. The power supply is configured to perform an at least partial compensation of a voltage variation caused by a load change using a voltage variation compensation mechanism which is activated in synchronism with one or more of the stimulus signals and/or in response to one or more response data signals from the device under test. Corresponding methods and a computer program are also described.

Abstract: A power supply comprises an output stage configured to provide a supply current, in order to obtain a supply voltage. The power supply also comprises a digital regulator configured to receive a reference voltage information and a measured voltage information and to provide a control signal. The power supply further comprises an inner analog control loop, wherein the inner analog control loop is configured to provide an analog feedback signal, which is based on the supply voltage, to the output stage, to make an analog regulation contribution to a regulation of the supply voltage. A method for supplying power to a load is also disclosed.

Abstract: A power supply is configured to perform an at least partial compensation of a voltage variation caused by a load change using a voltage variation compensation mechanism which is triggered in response to an expected load change. An Automated test equipment for testing a device under test comprises a power supply, which is configured to supply the device under test. The automated test equipment comprises a pattern generator configured to provide one or more stimulus signals for the device under test. The power supply is configured to perform an at least partial compensation of a voltage variation caused by a load change using a voltage variation compensation mechanism which is activated in synchronism with one or more of the stimulus signals and/or in response to one or more response data signals from the device under test. Corresponding methods and a computer program are also described.

Abstract: A power supply comprises an output stage configured to provide a supply current, in order to obtain a supply voltage. The power supply also comprises a digital regulator configured to receive a reference voltage information and a measured voltage information and to provide a control signal. The power supply further comprises an inner analog control loop, wherein the inner analog control loop is configured to provide an analog feedback signal, which is based on the supply voltage, to the output stage, to make an analog regulation contribution to a regulation of the supply voltage. A method for supplying power to a load is also disclosed.

Abstract: An assembly couples first and second backplanes together. The first backplane is configured to carry first electrical backplane signals among a first set of circuit boards. The second backplane is configured to carry second electrical backplane signals among a second set of circuit boards. The assembly includes a first switch configured to convey at least some of the first electrical backplane signals between circuit boards of the first set of circuit boards. The assembly further includes a second switch configured to convey at least some of the second electrical backplane signals between circuit boards of the second set of circuit boards. The assembly further includes a fiber optic cable joining the first and second switches together. The first and second switches are configured to exchange fiber optic signals through the fiber optic cable thus forming a cohesive backplane interconnect system between the first and second sets of circuit boards.

Abstract: A system having a plurality of processors, each one of the processors being adapted to issue a control signal and a processor ID code. Each one of the processors has: a unique, pre-assigned processor ID code, and a common software program. The software program operates to: receive the control signal and the processor ID code from the issuing one of the processors along with an indication of the one of the processors which issued the particular control signal and processor ID code; and test whether the received processor ID code is the same as the processor issuing the command and if so, generate one of the broadcast mode or uni-cast modes; otherwise, generate the other one of the broadcast or uni-cast modes.

Abstract: A data storage system wherein a host computer is coupled to a bank of disk drives through an interface. The interface has a plurality of directors and a memory interconnected by a buss. The directors control data transfer between the host computer and the bank of disk drives as such data passes through the memory. The interface includes a plurality of ESCON adapters, a front end portion of the directors being coupled between the host computer and the busses through the ESCON adapters. Each one of such adapters includes a plurality of adapter ports each one being coupled to a corresponding port of the host computer. Each one of the adapters also includes a plurality of adapter board gate arrays and a plurality of optic interfaces. Each one of the optic interfaces is coupled between a corresponding one of the adapter port and a corresponding one of the adapter board gate arrays. Each coupled optic interfaces and gate array provides a corresponding one of a plurality of channels for the data.