Patents by Inventor Rudy Octavius Sihombing
Rudy Octavius Sihombing has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10037988Abstract: A method of forming a HV lateral PNP BJT with a pulled back isolation structure and a polysilicon gate covering a part of the NW+HVNDDD base region and a part of the collector extension (HVPDDD) and the resulting device are provided. Embodiments include forming a DVNWELL in a portion of a p-sub; forming a HVPDDD in a portion of the DVNWELL; forming a LVPW in a portion of the HVPDDD; forming a first and a second NW laterally separated in a portion of the DVNWELL, the first and second NW being laterally separated from the HVPDDD; forming a N+ base, a P+ emitter, and a P+ collector in an upper portion of the first and second NW and LVPW, respectively; forming a STI structure between the P+ emitter and P+ collector in a portion of the DVNWELL, HVPDDD, and LVPW, respectively; and forming a SAB layer over the STI structure.Type: GrantFiled: August 24, 2017Date of Patent: July 31, 2018Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Yohann Frederic Michel Solaro, Rudy Octavius Sihombing, Tsung-Che Tsai, Chai Ean Gill
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Patent number: 9466730Abstract: The invention provides a semiconductor device, including: a substrate of a first conductivity type having an active region and a termination region; an epitaxial layer of the first conductivity type over the substrate; a plurality of first trenches and second trenches in the epitaxial layer; an implant blocker layer formed at bottoms of the first and second trenches; a liner of a second conductivity type different from the first conductivity type conformally formed along sidewalls of the first and second trenches; a dielectric material filled in the first and second trenches defining a plurality of first columns and a plurality second column, respectively; a gate dielectric layer over the epitaxial layer; two floating gates formed on the gate dielectric layer; a source region; an inter-layer dielectric layer; and a contact plug formed on the source region.Type: GrantFiled: January 17, 2014Date of Patent: October 11, 2016Assignee: Vanguard International Semiconductor CorporationInventors: Rahul Kumar, Manoj Kumar, Gene Sheu, Shao-Ming Yang, Rudy Octavius Sihombing, Chia-Hao Lee, Shang-Hui Tu
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Patent number: 9130033Abstract: The invention provides a semiconductor device, including: a semiconductor device includes: a substrate having a first conductivity type, including: a body region having the first conductivity type; a source region formed in the body region; a drift region having a second conductivity type adjacent to the body region, wherein the first conductivity type is opposite to the second conductivity type; and a drain region formed in the drift region; a trench formed in the substrate between the body and drift regions; a gate dielectric layer disposed adjacent to the trench; a liner lining the trench and adjoining with the gate dielectric layer; and a gate electrode formed over the gate dielectric layer and extending into the trench.Type: GrantFiled: December 3, 2013Date of Patent: September 8, 2015Assignee: Vanguard International Semiconductor CorporationInventors: Manoj Kumar, Priyono Tri Sulistyanto, Chia-Hao Lee, Rudy Octavius Sihombing, Shang-Hui Tu
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Publication number: 20150206966Abstract: The invention provides a semiconductor device, including: a substrate of a first conductivity type having an active region and a termination region; an epitaxial layer of the first conductivity type over the substrate; a plurality of first trenches and second trenches in the epitaxial layer; an implant blocker layer formed at bottoms of the first and second trenches; a liner of a second conductivity type different from the first conductivity type conformally formed along sidewalls of the first and second trenches; a dielectric material filled in the first and second trenches defining a plurality of first columns and a plurality second column, respectively; a gate dielectric layer over the epitaxial layer; two floating gates formed on the gate dielectric layer; a source region; an inter-layer dielectric layer; and a contact plug formed on the source region.Type: ApplicationFiled: January 17, 2014Publication date: July 23, 2015Applicant: Vanguard International Semiconductor CorporationInventors: Rahul KUMAR, Manoj KUMAR, Gene SHEU, Shao-Ming YANG, Rudy Octavius SIHOMBING, Chia-Hao LEE, Shang-Hui TU
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Patent number: 9076862Abstract: The invention provides a semiconductor device, including: a substrate having a first conductivity type, including: a body region having the first conductivity type; a source region formed in the body region; a drift region having a second conductivity type adjacent to the body region; and a drain region formed in the drift region; a multiple reduced surface field (RESURF) structure embedded in the drift region of the substrate; and a gate dielectric layer formed over the substrate; wherein the first conductivity type is opposite to the second conductivity type.Type: GrantFiled: February 4, 2013Date of Patent: July 7, 2015Assignee: Vanguard International Semiconductor CorporationInventors: Priyono Tri Sulistyanto, Rudy Octavius Sihombing, Chia-Hao Lee, Shang-Hui Tu
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Patent number: 9076887Abstract: A method for fabricating a semiconductor device is provided. A method for fabricating a semiconductor device includes providing a semiconductor substrate having a first conductive type. An epitaxy layer having the first conductive type is formed on the semiconductor substrate. First trenches are formed in the epitaxy layer. First insulating liner layers are formed on sidewalls and bottoms of the first trenches. A first dopant having the first conductive type dopes the epitaxy layer from the sidewalls of the first trenches to form first doped regions. A first insulating material is filled into the first trenches. Second trenches are formed in the epitaxy layer. Second insulating liner layers are formed on sidewalls and bottoms of the second trenches. A second dopant having a second conductive type dopes the epitaxy layer from the sidewalls of the second trenches to form second doped regions.Type: GrantFiled: May 4, 2012Date of Patent: July 7, 2015Assignee: Vanguard International Semiconductor CorporationInventors: Tsung-Hsiung Lee, Shang-Hui Tu, Rudy Octavius Sihombing
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Patent number: 9070763Abstract: A semiconductor device layout structure is provided. The semiconductor device layout structure includes an active region having a first conductivity type over a semiconductor substrate. The active region is provided with semiconductor devices formed thereon. A first super junction layout unit in the active region includes a first trench. A first doped region having a first conductivity type is formed surrounding the first trench. A second trench is formed surrounding the first doped region. A second doped region having a second conductivity type is formed surrounding the second trench. The first trench is laterally separated from the second trench through the first doped region and the second doped region in a plan view.Type: GrantFiled: March 26, 2014Date of Patent: June 30, 2015Assignee: Vanguard International Semiconductor CorporationInventors: Rudy Octavius Sihombing, Shang-Hui Tu
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Publication number: 20150155379Abstract: The invention provides a semiconductor device, including: a semiconductor device includes: a substrate having a first conductivity type, including: a body region having the first conductivity type; a source region formed in the body region; a drift region having a second conductivity type adjacent to the body region, wherein the first conductivity type is opposite to the second conductivity type; and a drain region formed in the drift region; a trench formed in the substrate between the body and drift regions; a gate dielectric layer disposed adjacent to the trench; a liner lining the trench and adjoining with the gate dielectric layer; and a gate electrode formed over the gate dielectric layer and extending into the trench.Type: ApplicationFiled: December 3, 2013Publication date: June 4, 2015Applicant: Vanguard International Semiconductor CorporationInventors: Manoj KUMAR, Priyono Tri SULISTYANTO, Chia-Hao LEE, Rudy Octavius SIHOMBING, Shang-Hui TU
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Patent number: 9048115Abstract: A method for fabricating a semiconductor device is provided. An epitaxial layer is grown on a substrate, wherein the epitaxial layer and the substrate have a first conductivity type. A trench is formed in the epitaxial layer. A barrier region is formed at a bottom of the trench. A doped region of a second conductivity type is formed in the epitaxial layer and surrounds sidewalls of the trench, wherein the barrier region prevents a dopant used for forming the doped region from reaching the epitaxial layer under the barrier region. The trench is filled with a dielectric material. A pair of polysilicon gates is formed on the epitaxial layer and on both sides of the trench.Type: GrantFiled: October 26, 2012Date of Patent: June 2, 2015Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Tsung-Hsiung Lee, Shang-Hui Tu, Gene Sheu, Neelam Agarwal, Karuna Nidhi, Chia-Hao Lee, Rudy Octavius Sihombing
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Publication number: 20140217501Abstract: The invention provides a semiconductor device, including: a substrate having a first conductivity type, including: a body region having the first conductivity type; a source region formed in the body region; a drift region having a second conductivity type adjacent to the body region; and a drain region formed in the drift region; a multiple reduced surface field (RESURF) structure embedded in the drift region of the substrate; and a gate dielectric layer formed over the substrate; wherein the first conductivity type is opposite to the second conductivity type.Type: ApplicationFiled: February 4, 2013Publication date: August 7, 2014Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Priyono Tri SULISTYANTO, Rudy Octavius SIHOMBING, Chia-Hao LEE, Shang-Hui TU
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Publication number: 20140117436Abstract: A method for fabricating a semiconductor device is provided. An epitaxial layer is grown on a substrate, wherein the epitaxial layer and the substrate have a first conductivity type. A trench is formed in the epitaxial layer. A barrier region is formed at a bottom of the trench. A doped region of a second conductivity type is formed in the epitaxial layer and surrounds sidewalls of the trench, wherein the barrier region prevents a dopant used for forming the doped region from reaching the epitaxial layer under the barrier region. The trench is filled with a dielectric material. A pair of polysilicon gates is formed on the epitaxial layer and on both sides of the trench.Type: ApplicationFiled: October 26, 2012Publication date: May 1, 2014Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Tsung-Hsiung LEE, Shang-Hui TU, Gene SHEU, Neelam AGARWAL, Karuna NIDHI, Chia-Hao LEE, Rudy Octavius SIHOMBING
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Publication number: 20140035029Abstract: A semiconductor device including a semiconductor substrate of a first conductivity type and an epitaxial layer of the first conductivity type disposed thereon is disclosed. Pluralities of first and second trenches are alternately arranged in the epitaxial layer. First and second doped regions of the first conductivity type are formed in the epitaxial layer and surrounding each first trench. A third doped region of a second conductivity type is formed in the epitaxial layer and surrounding each second trench. A first dopant in the first doped region has diffusivity larger than that of a second dopant in the second doped region. A method for fabricating a semiconductor device is also disclosed.Type: ApplicationFiled: August 2, 2012Publication date: February 6, 2014Inventors: Rudy Octavius Sihombing, Chia-Hao Lee, Tsung-Hsiung Lee, Shang-Hui Tu
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Patent number: 8642427Abstract: A semiconductor device including a semiconductor substrate of a first conductivity type and an epitaxial layer of the first conductivity type disposed thereon is disclosed. Pluralities of first and second trenches are alternately arranged in the epitaxial layer. First and second doped regions of the first conductivity type are formed in the epitaxial layer and surrounding each first trench. A third doped region of a second conductivity type is formed in the epitaxial layer and surrounding each second trench. A first dopant in the first doped region has diffusivity larger than that of a second dopant in the second doped region. A method for fabricating a semiconductor device is also disclosed.Type: GrantFiled: August 2, 2012Date of Patent: February 4, 2014Assignee: Vanguard International Semiconductor CorporationInventors: Rudy Octavius Sihombing, Chia-Hao Lee, Tsung-Hsiung Lee, Shang-Hui Tu
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Publication number: 20130149822Abstract: A method for fabricating a semiconductor device is provided. A method for fabricating a semiconductor device includes providing a semiconductor substrate having a first conductive type. An epitaxy layer having the first conductive type is formed on the semiconductor substrate. First trenches are formed in the epitaxy layer. First insulating liner layers are formed on sidewalls and bottoms of the first trenches. A first dopant having the first conductive type dopes the epitaxy layer from the sidewalls of the first trenches to form first doped regions. A first insulating material is filled into the first trenches. Second trenches are formed in the epitaxy layer. Second insulating liner layers are formed on sidewalls and bottoms of the second trenches. A second dopant having a second conductive type dopes the epitaxy layer from the sidewalls of the second trenches to form second doped regions.Type: ApplicationFiled: May 4, 2012Publication date: June 13, 2013Inventors: Tsung-Hsiung LEE, Shang-Hui Tu, Rudy Octavius Sihombing