Patents by Inventor Rudy van der Plassche

Rudy van der Plassche has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Resistor ladder interpolation for PGA and DAC
    Patent number: 7616144
    Abstract: A voltage interpolation circuit includes a resistive ladder connected between ground and a voltage input and having a plurality of resistors with voltage taps between the resistors. An amplifier (optionally) has first and second capacitors connected together at their respective first terminals and to an input of the amplifier. A first plurality of switches connect respective taps to a second terminal of the first capacitor. A second plurality of switches connect the respective taps to a second terminal of the second capacitor. An output voltage is interpolated by controlling the first and second pluralities of switches.
    Type: Grant
    Filed: September 18, 2007
    Date of Patent: November 10, 2009
    Assignee: Broadcom Corporation
    Inventors: Jan Mulder, Franciscus Maria Leonardus van der Goes, Jan Westra, Rudy van der Plassche
  • High Speed Latch Comparators
    Publication number: 20080143391
    Abstract: In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.
    Type: Application
    Filed: February 29, 2008
    Publication date: June 19, 2008
    Applicant: Broadcom Corporation
    Inventors: Klass BULT, Rudy VAN DER PLASSCHE, Jan MULDER
  • Resistor Ladder Interpolation for PGA and DAC
    Publication number: 20080088493
    Abstract: A voltage interpolation circuit includes a resistive ladder connected between ground and a voltage input and having a plurality of resistors with voltage taps between the resistors. An amplifier (optionally) has first and second capacitors connected together at their respective first terminals and to an input of the amplifier. A first plurality of switches connect respective taps to a second terminal of the first capacitor. A second plurality of switches connect the respective taps to a second terminal of the second capacitor. An output voltage is interpolated by controlling the first and second pluralities of switches.
    Type: Application
    Filed: September 18, 2007
    Publication date: April 17, 2008
    Applicant: Broadcom Corporation
    Inventors: Jan MULDER, Franciscus van der GOES, Jan WESTRA, Rudy van der PLASSCHE
  • Resistor ladder interpolation for PGA and DAC
    Patent number: 7271755
    Abstract: A voltage interpolation circuit includes a resistive ladder connected between ground and a voltage input and having a plurality of resistors with voltage taps between the resistors. An amplifier (optionally) has first and second capacitors connected together at their respective first terminals and to an input of the amplifier. A first plurality of switches connect respective taps to a second terminal of the first capacitor. A second plurality of switches connect the respective taps to a second terminal of the second capacitor. An output voltage is interpolated by controlling the first and second pluralities of switches.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: September 18, 2007
    Assignee: Broadcom Corporation
    Inventors: Jan Mulder, Franciscus Maria Leonardus van der Goes, Jan Westra, Rudy van der Plassche