Abstract: A circuit is provided for multiplexing data packets, each having sets of n digital words and a residual set of r digital words. The multiplexing arrangement includes an output terminal (OUT), input memory units (RAM0-RAM3) each to receive and to store the data packets in memory portions and each to store n digital words, and a multiplexer (MUX) coupled to the input memory units (RAM0-RAM3) and to transfer the data packets thereof to the output terminal (OUT). The circuit also includes a register (RGN) and a residual register (RGR), each connected in parallel to the input memory units (RAM0-RAM3). The register (RGN) reads and transfers the sets of n digital words to the multiplexer (MUX). The residual register (RGR) reads and transfers the residual set of r digital words to the multiplexer (MUX). The multiplexer (MUX) combines the set of n digital words and the residual set of r digital words, forming a combined set, and providing at least a portion of the combined set to the output terminal (OUT).