Patents by Inventor Ruediger Brede

Ruediger Brede has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit memory device responsive to word line/bit line short-circuit
    Patent number: 7697354
    Abstract: An integrated circuit memory device includes a memory array with associated word lines and bit lines. A switching arrangement is connected between a word line and a first voltage source that selectively connects the word line to the first voltage source, and also is responsive to a short-circuit between the word line and the bit line.
    Type: Grant
    Filed: May 30, 2007
    Date of Patent: April 13, 2010
    Assignee: Qimonda AG
    Inventors: Ruediger Brede, Rainer Bartenschlager, Marcus Unertl
  • CURRENT REDUCTION WITH WORDLINE BIT LINE SHORT-CIRCUITS IN DRAMS AND DRAM DERIVATIVES
    Publication number: 20080298149
    Abstract: An integrated circuit memory device includes a memory array with associated word lines and bit lines. A switching arrangement is connected between a word line and a first voltage source that selectively connects the word line to the first voltage source, and also is responsive to a short-circuit between the word line and the bit line.
    Type: Application
    Filed: May 30, 2007
    Publication date: December 4, 2008
    Applicant: QIMONDA AG
    Inventors: Ruediger Brede, Rainer Bartenschlager, Marcus Unertl
  • Method and apparatus for optimizing the functioning of DRAM memory elements
    Patent number: 7072233
    Abstract: In the method for modifying a default time duration between an execution instant of a second operation and an earlier execution instant of a first operation executed earlier in a memory element, wherein the memory element is operable in a test operation mode and a normal operation mode, at first a real time duration in the memory element is determined and provided during the test operation mode, wherein the real time duration is chosen so that a performance parameter of the memory element, when using the real time duration between the execution instants of the first and second operations, improves over a situation in which the default time duration between the execution instants of the first and second operations is used. Then, the default time duration is changed in direction of the real time duration during the test operation mode to obtain a modified default time duration.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: July 4, 2006
    Assignee: Infineon Technologies AG
    Inventors: Ruediger Brede, Dominique Savignac, Helmut Fischer
  • Method and apparatus for optimizing the functioning of DRAM memory elements
    Publication number: 20050002245
    Abstract: In the method for modifying a default time duration between an execution instant of a second operation and an earlier execution instant of a first operation executed earlier in a memory element, wherein the memory element is operable in a test operation mode and a normal operation mode, at first a real time duration in the memory element is determined and provided during the test operation mode, wherein the real time duration is chosen so that a performance parameter of the memory element, when using the real time duration between the execution instants of the first and second operations, improves over a situation in which the default time duration between the execution instants of the first and second operations is used. Then, the default time duration is changed in direction of the real time duration during the test operation mode to obtain a modified default time duration.
    Type: Application
    Filed: May 21, 2004
    Publication date: January 6, 2005
    Inventors: Ruediger Brede, Dominique Savignac, Helmut Fischer