Abstract: A crosspoint matrix has matrix input lines which lead via pairs of switching elements to matrix output lines having, respectively, two signal conductors which are respectively connectible to a reference potential source via a precharging transistor controlled by a precharging clock and which have signal inputs of differential amplifier with a trigger behavior connectible thereto. The pair of switching elements respectively comprise two input transistors that have their control electrodes connected to a signal conductor of the appertaining matrix input line and form a series circuit with a respective switching transistor leading to the one or, respectively, other output signal conductor, a logic element that is respectively oppositely controlled by the precharging clock is inserted into the input lines and, in the switching elements, the ends of the series circuits facing away from the matrix output line are directly connected to the appertaining terminal of the operating voltage source.

Abstract: In a broad band signal spaced coupling device comprising a cross point matrix whose switching matrix elements are respectively controllable by a decoder-controlled, cross point-associated memory cell, the cross points are respectively formed with a complementary metal-oxide-semiconductor transfer gate and the useful signal input of each such gate is preceded by a complementary metal-oxide-semiconductor inverter.

Abstract: Broadband signal switching equipment in a switching point matrix having matrix input lines connected via switching element couples, to matrix output lines having respectively two signal conductors. The two signal conductors are connected with signal inputs of a differential amplifier with a trigger characteristic. The two signal conductors of each matrix output line are connected with the operating potential source via a respective precharge transistor. The switching element couples respectively have two auxiliary transistors of different channel types, which are connected by their control electrode to the only signal conductor of the appertaining matrix input line and which form a series connection respectively with one switch transistor preferably of the same channel type. The output terminals of successive switching elements of a matrix output line are respectively connected to the signal conductors thereof in an alternating fashion.

Abstract: In a broadband signal switching equipment having crosspoint matrix using FET technology devices crosspoint-associated storage memory cells that control switching elements are each formed with two cross-coupled n-MOS inverter circuits each of which has its input side connected via a selection transistor to a selection line that carries a non-inverted and an inverted selection signal of one selection direction, respectively. Both selection transistors receive on their control electrodes the selection signal of the other selection direction. The control electrodes of two load transistors of the two cross-coupled n-channel inverter circuits are connected to the selection line that carries the inverted selection clock signal of the other selection direction.

Abstract: In a crosspoint matrix in which matrix input lines respectively comprising two signal conductors connected to differential outputs of differential line drivers lead to matrix output lines likewise each comprising two signal conductors and having signal outputs of a differential amplifier which has a trigger behavior connected thereto and wherein the two signal conductors of each matrix output line are respectively connectible via a pre-charging transistor to the operating voltage source, these two signal conductors also being connected to one another via a shunt transistor for an early balancing of potential. A pre-charging transistor, in addition to a sampling transistor, can be provided at a pseudo-grounded line associated to a matrix line.

Abstract: In a crosspoint matrix, column lines are formed by two signal conductors connected to difference outputs of differential line drivers which are connected by switch element pairs of transistors to row lines, the row lines also each formed by two signal conductors. The two signal conductors of each row line are respectively connected to two outputs of a differential amplifier operating in a trigger mode. Each of the switch elements, includes a switching transistor having its control electrode charged with a through-connect or an inhibit signal and having its main electrode connected to an matrix output line and an auxiliary transistor forming a series circuit with the switching transistor. The auxiliary transistor has its control electrode connected to a matrix input line and its main electrode connected away from the series circuit connected to ground by a sampling transistor. The matrix output conductor is connected to an operating potential by way of a precharging transistor.

Abstract: A broadband signal cross point switching equipment comprises a cross point matrix having FET switch elements formed with a switching transistor and a holding circuit for providing a through-connect or inhibit signal. The matrix has input lines and output lines and the switching transistor includes a main electrode connected to the respective output line. The switch elements each comprise an auxiliary transistor forming a series circuit with the switching transistor and including a control electrode which is connected to the appertaining matrix input line and a main electrode, facing away from the series circuit, connected by way of a sampling transistor to one terminal of the operating voltage source, to whose other terminal the respective matrix output line is connected by way of a precharging transistor.

Abstract: In a broadband signal space switching device comprising a cross point matrix whose switching elements are respectively controlled by holding storage cells selected by cross point-associated means in two coordinate directions by selection decoders, the holding storage cells being formed by bistable D flip-flops constructed in CMOS technology whose D inputs are connected to the respective decoder output of the row decoder charged with a cross point row address and an address clock signal and whose clock inputs are connected to the corresponding decoder output of the column decoder respectively charged with a cross point column address and an address clock signal.

Abstract: In a broadband signal space switching apparatus, respective switching elements are controlled by respective decoder-controlled, crosspoint-associated memory cell and are respectively formed with a CMOS NOR gate and a CMOS NAND gate, each of which has a respective input connected to the appertaining signal input line and another respective input connected to the output or, respectively, to the complementary output of the memory cell. The two inputs of a CMOS push-pull output circuit are connected to the output of the CMOS NAND gate and to the output of the CMOS NOR gate, the output of the CMOS push-pull output circuit forming the output of the switching element. The two source electrodes of the CMOS push-pull output circuit are fed by two feed voltage sources corresponding to the CMOS logic levels.

Abstract: An address buffer is disclosed in MOS technology with an address memory circuit exhibiting an address input driven via a transfer signal and having two complementary address outputs and two complementary signal outputs of high signal level. An isolating amplifier is provided with a following-connected output stage. The isolating amplifier is driven via a control clock pulse and supplies complementary control signals. It also has two parallel paths each consisting of the driven segments of two transistors. These parallel paths are connected to the drive clock pulse at a first common node and are connected to a base voltage source at a second common node. The first transistor of each parallel path is driven via a respective high signal level signal output of the address memory circuit and the second transistor of each parallel path is driven via a respective address output of the address memory circuit which is inverse to the high level signal output.

Abstract: A decoder circuit arrangement with MOS transistors includes a decoder circuit and an output stage. The output stage includes a driver transistor which emits a selection signal, in accordance with a decoder signal emitted from the decoder circuit, and includes a shunt transistor having a controlled path connected between the output of the decoder circuit and the output of the output stage and a control input which is supplied with the selection signal. An additional transistor has a controlled path connected between the output of the output stage and a fixed potential and a control input which is driven by a timing signal which renders the additional transistor conductive, at least during the time in which the selection signal is not present.

Abstract: A MOS storage module has MOS transistor storage cells disposed between word and bit lines. A weighting network is symmetrically connected in each pair of bit lines for evaluating read signals. The weighting networks are arranged in a column with the storage cells which are connected to first inputs of the weighting networks form a first storage cell field and the storage cells which are connected to second inputs of the weighting networks form a second storage cell field and all storage cell fields on the storage module are disposed on one side of the column of weighting networks.

Abstract: A system is disclosed for addressing a MOS store containing MOS transistor storage cells. Address signals are amplified, inverted and intermediately stored. Negated and non-negated address signals are fed to a decoder circuit connected by drive lines to the storage cells. The decoder circuit selects a drive line depending upon the prevailing address signals. The decoder circuit is provided as a preliminary decoder circuit and a post decoder circuit. The preliminary decoder circuit has a plurality of stages wherein each stage is supplied with address signals in negated and non-negated form. Output lines of the preliminary decoder stages are connected to the post decoder circuit. Drive lines connect the storage cells to the post decoder circuit. Logic linking elements are provided in the post decoder circuit for logic linking these drive lines to the output lines of the preliminary decoder stages.

Abstract: A circuit arrangement for monitoring the function of a dynamic decoder circuit which comprises at least parallel-connected decoder transistors, a pre-charging transistor, and an end stage which samples the output signal of the decoder transistors, is disclosed in which for simulating the decoder circuit, two discharge transistors are connected in parallel and have control inputs which are supplied with address signals in inverted form and in non-inverted form and whose node, which is formed by the one connection point, is precharged in that it is connected to a further transistor. In order to simulate the capacitance existing at the corresponding connection point of the parallel-connected decoder transistors of a decoder circuit, a varactor is connected to the node and the node is also connected to the further circuit elements provided in the decoder circuit between the decoder transistors and the end stage.