Abstract: An electronic device comprising a first supply voltage domain, a second supply voltage domain and a low drop output voltage regulator (LDO) coupled to receive a supply voltage of the first supply voltage domain and to provide a supply voltage of the second supply voltage domain and the LDO being configured to be switched into a first state for providing and maintaining the supply voltage of the second supply voltage domain and into a second state for providing a high impedance output to the second supply voltage domain. The electronic device includes a comparator coupled to monitor the first supply voltage level at a first supply voltage node and to switch the LDO from the first state to the second state.

Abstract: The invention relates to an electronic device which comprises a comparator coupled to monitor a first supply voltage level at a first supply voltage node. The comparator comprises a differential input transistor stage having one input coupled to the first supply voltage node and the other input coupled to receive a reference voltage level, a first current source configured to supply a current of a first magnitude, a second current source configured to supply a current of a second magnitude, and a capacitor. The first magnitude is greater than the second magnitude and the first current source is coupled with one side to the differential input stage for supplying the differential input stage and with the other side to a first node. The second current source is coupled with one side to the first node and with the other side to a second supply voltage node having a second supply voltage level and the capacitor is coupled with one side to the first node and with the other side to the first supply voltage node.

Abstract: The invention relates to an electronic device which comprises a voltage regulator for providing a regulated output voltage to an electronic circuit and a control stage coupled to control the voltage regulator. The control stage is further configured to detect a request for a change of a system configuration of the electronic circuit coupled to receive the output voltage of the voltage regulator, to determine an activity factor of the electronic circuit for the requested system configuration, to determine a system clock frequency of a system clock of the electronic circuit, to determine a required current drive level of the voltage regulator based on the activity factor, the system clock frequency or the product of both, and to adjust the current drive level of the voltage regulator to the requested current drive level.

Abstract: The invention relates to an electronic device which comprises a comparator coupled to monitor a first supply voltage level at a first supply voltage node. The comparator comprises a differential input transistor stage having one input coupled to the first supply voltage node and the other input coupled to receive a reference voltage level, a first current source configured to supply a current of a first magnitude, a second current source configured to supply a current of a second magnitude, and a capacitor. The first magnitude is greater than the second magnitude and the first current source is coupled with one side to the differential input stage for supplying the differential input stage and with the other side to a first node. The second current source is coupled with one side to the first node and with the other side to a second supply voltage node having a second supply voltage level and the capacitor is coupled with one side to the first node and with the other side to the first supply voltage node.

Abstract: A tristate buffer circuit includes a tristate buffer switchable into a high impedance state in response to configuration signal, a delay stage delays the an input signal to the tristate buffer and a gating stage having inputs for the input signal, a delayed input signal and an asynchronous tristate control signal and an output supplying the configuration signal to the tristate buffer. The gating stage sets the configuration signal to the high impedance mode only when the tristate control signal is set and the input signal and the delayed input signal have logic levels indicating that no signal transition of the input signal propagates within the delay stage. Depending upon signal polarity, the input signal and the delayed input signal are required to have the same digital state or opposite digital states.

Abstract: An equalization circuit that allows particularly for lowpass filtering by transmission lines comprises a compensating equalizer controlled according to whether the edges between bits in the data waveform are early or late. Adjusting the equalization causes edges to appear in the same place, whereas if the adjustment is incorrect certain edges will be late and certain edges will be early depending on the history of “1”s and “0”s in the data stream. This is an effect of so-called intersymbol interference. The control mechanism includes circuits for recognizing patterns of “1”s and “0”s in the recent history of the data waveform whose occurrence is used to trigger the adjustment of the equalizer.

Abstract: An electronic device has an LDO regulator for varying loads. The LDO regulator includes a primary supply node coupled to a primary voltage supply. An output node provides a secondary supply voltage and a load current. A bias current source generates a bias current. A gain stage coupled to the bias current source increases the maximum available load current. The gain stage includes a first MOS transistor biased in weak inversion coupled to a current mirror which mirrors the drain current through the first MOS transistor to the output node. The gate-source voltage of the first MOS transistor increases in response to a decreasing secondary supply voltage level at the output node to increase the available load current.

Abstract: The present invention switches between a first clock signal (CLK0) and a second clock signal (CLK1). Each input signal is buffered by a corresponding tristate buffer (TBUF0, TBUF1). A multiplexer (MUX) receives the tristate buffer outputs and selects one clock signal in response to a multiplexer control signal (MUX_SEL). A control stage (CONTROL) received a clock selection signal (SEL) and provides multiplexer control signal (MUX_SEL). A change in multiplexer control signal (MUX_SEL) is triggered by a next edge of target clock (CLK1) following a delay. This prevents glitches in the output signal.

Abstract: The present invention switches between a first clock signal (CLK0) and a second clock signal (CLK1). Each input signal is buffered by a corresponding tristate buffer (TBUF0, TBUF1). A multiplexer (MUX) receives the tristate buffer outputs and selects one clock signal in response to a multiplexer control signal (MUX_SEL). A control stage (CONTROL) received a clock selection signal (SEL) and provides multiplexer control signal (MUX_SEL). A change in multiplexer control signal (MUX_SEL) is triggered by a next edge of target clock (CLK1) following a delay. This prevents glitches in the output signal.

Abstract: An electronic device has an LDO regulator for varying loads. The LDO regulator includes a primary supply node coupled to a primary voltage supply. An output node provides a secondary supply voltage and a load current. A bias current source generates a bias current. A gain stage coupled to the bias current source increases the maximum available load current. The gain stage includes a first MOS transistor biased in weak inversion coupled to a current mirror which mirrors the drain current through the first MOS transistor to the output node. The gate-source voltage of the first MOS transistor increases in response to a decreasing secondary supply voltage level at the output node to increase the available load current.

Abstract: A tristate buffer circuit includes a tristate buffer switchable into a high impedance state in response to configuration signal, a delay stage delays the an input signal to the tristate buffer and a gating stage having inputs for the input signal, a delayed input signal and an asynchronous tristate control signal and an output supplying the configuration signal to the tristate buffer. The gating stage sets the configuration signal to the high impedance mode only when the tristate control signal is set and the input signal and the delayed input signal have logic levels indicating that no signal transition of the input signal propagates within the delay stage. Depending upon signal polarity, the input signal and the delayed input signal are required to have the same digital state or opposite digital states.

Abstract: An equalization circuit that allows particularly for lowpass filtering by transmission lines comprises a compensating equalizer controlled according to whether the edges between bits in the data waveform are early or late. Adjusting the equalization causes edges to appear in the same place, whereas if the adjustment is incorrect certain edges will be late and certain edges will be early depending on the history of “1”s and “0”s in the data stream. This is an effect of so-called intersymbol interference. The control mechanism includes circuits for recognizing patterns of “1”s and “0”s in the recent history of the data waveform whose occurrence is used to trigger the adjustment of the equalizer.