Abstract: Techniques are disclosed for procuring items using a central computer system in a distributed network of computer systems. In one general aspect, the invention provides for receiving, at a central computer system, a first purchase request for a first item to be procured. The first purchase request is received from a first computer system in a network of computer systems and includes a first item category identifier that describes the first item. A second computer system in the network is selected based on the first item category identifier so that a purchase document may be created in the second computer system. The creation of the purchase document in the second computer system is controlled by the central computer system.

Abstract: A device for fastening eyeglasses is improved such that the lenses can be adjusted to the eyes of the mask user independently from one another. An ear piece (6) bent in an L-shaped pattern is provided. The earpiece is arranged on a holding element (4), which is located at an edge (1) of an eye-protecting lens (2). A frame (9) with a lens (10) is fastened at the other free end of the ear piece (6) by a displaceable bracket (8).

Abstract: A self-supporting and self-adhesive molded article is described having a glass transition temperature of less than 10° C. and containing a binder and an aliphatic or cyoaliphatic nonionic surfactant. The binder may contain at least one addition polymer or addition copolymer. The article is redetachable from the material surfaces to which it may be adhered. Thus, the article may be attached, detached and reattached to a wall or cabinet surface and may have paper or other light weight, decorative material attached, detached and reattached to it. The detachment and reattachment process maybe repeated numerous times, particularly with intervening cleaning of the surface of the self-supporting and self-adhesive molded article.

Abstract: A container for the gastight sealing of a respirator. The container has two container shells (1, 2) abutting on front surfaces with a circumferential sealing element. The container second container shell (2) is provided with a handle (3) mounted at two opposite points of rotation (6). The handle (3) has a lever arm (5), which engages in the first container shell (1) in the closed position of the container. In the closed position of the container, the handle (3) preferably engages in an additional bracket (4) that is detachably connected to the first container shell (1).

Abstract: The invention concerns a polyacrylamide-containing composition which is characterized in that it has a molecular weight of between 2,000 and 8,000 g/mol, determined by means of gel permeation chromatography (GPC), and as a 15% aqueous solution still has a Brookfield viscosity of between 100 and 500 mPas at 25° C. The invention further concerns the use of this polyacrylamide-containing composition for the flat bonding of water absorbent and hard surfaces and for equipping plastic surfaces with non-slip protection.

Abstract: The proposed process for bonding together two substrates with an anhydrous or low-water-content partially crystalline adhesive which is solid at room temperature is characterized in that the adhesive is first activated by internal and/or external friction. The substrates are then joined together with the adhesive between them. When allowed to stand, the structure attains its final strength after a period of between a few seconds to a few days. The friction destroys the crystalline structure and causes the adhesive to become gluey, and re-crystallization gives it its final strength and eliminates the gluey quality. The adhesive is based preferably on polyester or polyurethane and used preferably in the form of a gum stick without impermeable packaging. It is especially suitable for bonding paper, since it does not cause corrugation.

Abstract: An optoelectronic coupling element having a light-emitting semiconductor device serving as transmitter chip, and a light-receiving semiconductor device serving as a receiver chip, and are firmly connected together through an optic coupling medium (3). This compact coupling element is to have a defined degree of coupling largely independent of the housing and is to be suitable for simple conductor tape mounting. To this end, the coupling medium (3) is an insulating transparent intermediate layer, and the light-emitting semiconductor device (1), the coupling element (3) and the light-receiving semiconductor device (2) are directly laminated one on the other. This optoelectronic coupler is used in particular as an optocoupler for signal transmission.

Abstract: A time base circuit feeds a frequency divider via a current amplifier. A current supply circuit is connected to supply the current amplifier and the frequency divider. The current supply may also be connected to supply the time base circuit; otherwise the time base circuit is responsive to electromagnetic radiation for supplying its own current.

Abstract: A system is disclosed for coupling electrically isolated circuits in a monolithic integrated circuit. A signal coupler is integrated on a chip together with a primary circuit and a secondary circuit which is to be coupled to the primary circuit. The signal coupler comprises an integrated coupling capacitor which consists of a coplanar conductor path arrangement embedded into a passivation layer, the passivation layer being applied to an insulating substrate, preferably sapphire.

Abstract: A Schottky-transistor-logic arrangement is disclosed which comprises a highly doped semiconductor substrate of one conductivity type. An epitaxial layer of the same conductivity type is formed on the substrate. A deep-implanted doped zone of the other conductivity type is located in the epitaxial layer in a plane spaced below the outer surface of said epitaxial layer and lying substantially parallel thereto. A load transistor and an output transistor are formed by constructing the arrangement so that the buried layer provides the base of the load transistor and the emitter of the output transistor. The emitter of the load transistor is provided by a portion of the epitaxial layer which lies below the deep-implanted doped zone. The collector of the load transistor and the base of the output transistor are provided by the portion of the epitaxial layer which lies above the deep-implanted zone. A Schottky electrode on the outer surface of the epitaxial layer provides the collector of the output transistor.

Abstract: An integrated current supply circuit is disclosed which utilizes a sub-circuit having a lambda-like current-voltage curve. Such a sub-circuit comprises a first field effect transistor whose source-drain path is connected to a series circuit formed from a load element and a second field effect transistor. The gate of the first field effect transistor is connected to the connection point of the load element and the second field effect transistor. A gate of the second FET leads either directly or via a voltage divider to the drain-side terminal of the series circuit. A capacitor is provided which is connected across output terminals of the circuit. The series circuit of the lambda sub-circuit is connected in parallel with input terminals, and the first FET connects between one of the input terminals and one of the output terminals.

Abstract: An arrangement is provided for supplying integrated injection logic (I.sup.2 L) circuits with differing currents. A first injector path is formed by a connection between an external supply voltage source and injectors of first I.sup.2 L circuits to be supplied with a first current. The first injector path is connected to the injecting emitter of a current hogging injection logic (CHIL) arrangement and a first input of the CHIL arrangement is connected to a second injector path formed by the connection to injectors of second I.sup.2 L circuits to be supplied with a second current.

Abstract: An amplifier stage is provided for supplying differing currents to integrated injection logic I.sup.2 L circuits. The amplifier stage has a current hogging injection logic input CHIL gate, at least one further gate, and a CHIL output gate. Each of the gates has an injecting emitter, an output and an input. First I.sup.2 L circuits connected to a first injector path connect with the input of the CHIL input gate. Second I.sup.2 L circuits having a second injector path connect with an output of the CHIL output gate. The gate provided between the input and output CHIL gates is provided as a single I.sup.2 L gate, dual I.sup.2 L gates, or the combination of an I.sup.2 L gate and a CHIL gate.

Abstract: A lateral bipolar transistor has a silicon film which is epitaxially deposited on an electrical insulating substrate. The silicon film is doped with impurities of a first conductivity type such that a portion of the film may be utilized as a base zone. Within the base zone an emitter zone and a collector zone are formed of the second conductivity type. A highly doped zone of the second conductivity type is produced by deep implantation at a position which is contiguous and below the base zone, below the emitter and collector zones, and at a boundary between the silicon film and the electrical insulating substrate. An insulating zone over the film and a conductive layer over the base zone are also provided. The conductive film over the base zone together with the highly doped zone below and contiguous with the base minimize surface recombination and increase device gain.

Abstract: A circuit arrangement CHL technique (current hogging logic) includes individual CHL arrangements each having an emitter, control collectors and an output collector and arranged within an epitaxial layer. The individual CHL arrangements are complementary with respect to one another, and arrangement of one conductivity type being directly integrated in the epitaxial layer and the arrangement which is complementary thereto being integrated in a basin in the epitaxial layer, the basin being doped opposite to the epitaxial layer.

Abstract: A logic circuit has the individual elements arranged in a semiconductor layer. The elements are in the form of field effect transistors having a multiple gate and bipolar transistors having a multiple emitter. The multiple gates of the field effect transistor represent the inputs of the fundamental logic circuit, and at least one emitter of the multiple emitters of the bipolar transistor represents the output of the fundamental logic circuit. The elements are arranged in the semiconductor layer in such a manner that a first supply voltage potential can be connected to the semiconductor layer. One configuration of the multiple gates of the field effect transistor identifies the circuit as a NAND circuit, while another configuration of the gates identifies the circuit as a NOR circuit. An additional element, a bipolar transistor, may be formed in the semiconductor layer and be connected to an emitter of the multiple emitter transistor to provide a power output stage in a Darlington configuration.