Abstract: A method is provided for testing an integrated circuit comprising multiple cores, with at least two cores having different associated first and second clock signals of different frequencies. A test signal is provided using a clocked scan chain clocked at a test frequency (TCK). A transition is provided in a clock circuit reset signal (clockdiv_rst) which triggers the operation of a clock divider circuit (44) which derives the first and second clock signals (clk_xx, clk_yy, clk_zz) from an internal clock (40) of the integrated circuit. The first and second clock signals thus start at substantially the same time, and these are used during a test mode to perform a test of the integrated circuit. After test, the test result is output using the clocked scan chain clocked at the test frequency (TCK).

Abstract: A method is provided for testing an integrated circuit comprising multiple cores, with at least two cores having different associated first and second clock signals of different frequencies. A test signal is provided using a clocked scan chain clocked at a test frequency (TCK). A transition is provided in a clock circuit reset signal (clockdiv_rst) which triggers the operation of a clock divider circuit (44) which derives the first and second clock signals (clk_xx, clk_yy, clk_zz) from an internal clock (40) of the integrated circuit. The first and second clock signals thus start at substantially the same time, and these are used during a test mode to perform a test of the integrated circuit. After test, the test result is output using the clocked scan chain clocked at the test frequency (TCK).

Abstract: In an arrangement for testing an integrated circuit comprising at least two circuit sections (1, 2) which in normal operation operate with at least two different clock signals, a minimal number of test runs for testing the integrated circuit is required because the integrated circuit to be tested is formed in such a way that each clock signal can be individually switched on and off during a test by test software provided in the arrangement, a software model of the circuit to be tested is provided in the arrangement, which software model comprises an X generator (38, 40) for those circuit components (33, 35) whose mode of operation is influenced by a plurality of clock signals and their skew behavior, which X generator is activated and supplies an X signal when more than one clock signal influencing the mode of operation of the circuit components (33, 35) during testing is activated, while, during testing, the test software initially activates all clock signals and evaluates test results for those circuit comp

Abstract: In an arrangement for testing an integrated circuit comprising at least two circuit sections (1, 2) which in normal operation operate with at least two different clock signals, a minimal number of test runs for testing the integrated circuit is required because the integrated circuit to be tested is formed in such a way that each clock signal can be individually switched on and off during a test by test software provided in the arrangement, a software model of the circuit to be tested is provided in the arrangement, which software model comprises an X generator (38, 40) for those circuit components (33, 35) whose mode of operation is influenced by a plurality of clock signals and their skew behavior, which X generator is activated and supplies an X signal when more than one clock signal influencing the mode of operation of the circuit components (33, 35) during testing is activated, while, during testing, the test software initially activates all clock signals and evaluates test results for those circuit comp