Abstract: An embedded capacitor structure in a circuit board and a method for fabricating the same are proposed. The circuit board is formed with a first circuit layer on at least one surface thereof, wherein the first circuit layer has at least one first electrode plate for the capacitor structure. Then, a dielectric layer is formed on the first circuit layer and made flush with the first circuit layer. The dielectric layer has a relatively low dielectric constant and good fluidity to effectively fill the spaces between patterned traces of the first circuit later. A capacitive material is deposited on the dielectric layer and the first circuit layer. Finally, a second circuit layer is formed on the capacitive material and has at least one second electrode plate corresponding to the first electrode plate, together with the capacitive material disposed in-between, to form the capacitor structure.

Abstract: A pre-solder structure on a semiconductor package substrate and a method for fabricating the same are proposed. A plurality of conductive pads are formed on the substrate, and a protective layer having a plurality of openings for exposing the conductive pads is formed over the substrate. A conductive seed layer is deposited over the protective layer and openings. A patterned resist layer is formed on the seed layer and has openings corresponding in position to the conductive pads. A plurality of conductive pillars and a solder material are deposited in sequence in each of the openings. The resist layer and the seed layer not covered by the conductive pillars and the solder material are removed. The solder material is subject to a reflow-soldering process to form pre-solder bumps covering the conductive pillars.

Abstract: An embedded capacitor structure in a circuit board and a method for fabricating the same are proposed. The circuit board is formed with a first circuit layer on at least one surface thereof, wherein the first circuit layer has at least one first electrode plate for the capacitor structure. Then, a dielectric layer is formed on the first circuit layer and made flush with the first circuit layer. The dielectric layer has a relatively low dielectric constant and good fluidity to effectively fill the spaces between patterned traces of the first circuit later. A capacitive material is deposited on the dielectric layer and the first circuit layer. Finally, a second circuit layer is formed on the capacitive material and has at least one second electrode plate corresponding to the first electrode plate, together with the capacitive material disposed in-between, to form the capacitor structure.

Abstract: A pre-solder structure on a semiconductor package substrate and a method for fabricating the same are proposed. A plurality of conductive pads are formed on the substrate, and a protective layer having a plurality of openings for exposing the conductive pads is formed over the substrate. A conductive seed layer is deposited over the protective layer and openings. A patterned resist layer is formed on the seed layer and has openings corresponding in position to the conductive pads. A plurality of conductive pillars and a solder material are deposited in sequence in each of the openings. The resist layer and the seed layer not covered by the conductive pillars and the solder material are removed. The solder material is subject to a reflow-soldering process to form pre-solder bumps covering the conductive pillars.

Abstract: A substrate with stacked vias and fine circuits and a method for fabricating the substrate are proposed. A core layer is formed with a metal layer respectively on upper and lower surfaces thereof, and at least one through hole. A first insulating layer is applied over the metal layer on the upper surface of the core layer and selectively formed with at least one first opening for exposing the metal layer. A metal layer is formed within the first opening, and a second insulating layer is applied over the first insulating layer and formed with a plurality of second openings, wherein the metal layer within the first opening is exposed via at least one second opening. After a conductive layer is applied over the second insulating layer and within the second openings, a metal layer is formed within the second openings. Finally, the conductive layer is removed by micro-etching.

Abstract: An embedded capacitor structure in a circuit board and a method for fabricating the same are proposed. The circuit board is formed with a first circuit layer on at least one surface thereof, wherein the first circuit layer has at least one first electrode plate for the capacitor structure. Then, a dielectric layer is formed on the first circuit layer and made flush with the first circuit layer. The dielectric layer has a relatively low dielectric constant and good fluidity to effectively fill the spaces between patterned traces of the first circuit later. A capacitive material is deposited on the dielectric layer and the first circuit layer. Finally, a second circuit layer is formed on the capacitive material and has at least one second electrode plate corresponding to the first electrode plate, together with the capacitive material disposed in-between, to form the capacitor structure.

Abstract: A substrate with stacked vias and fine circuits and a method for fabricating the substrate are proposed. A core layer is formed with a metal layer respectively on upper and lower surfaces thereof, and at least one through hole. A first insulating layer is applied over the metal layer on the upper surface of the core layer and selectively formed with at least one first opening for exposing the metal layer. A metal layer is formed within the first opening, and a second insulating layer is applied over the first insulating layer and formed with a plurality of second openings, wherein the metal layer within the first opening is exposed via at least one second opening. After a conductive layer is applied over the second insulating layer and within the second openings, a metal layer is formed within the second openings. Finally, the conductive layer is removed by micro-etching.

Abstract: A substrate with stacked vias and fine circuits and a method for fabricating the substrate are proposed. A core layer is formed with a metal layer respectively on upper and lower surfaces thereof, and at least one through hole. A first insulating layer is applied over the metal layer on the upper surface of the core layer and selectively formed with at least one first opening for exposing the metal layer. A metal layer is formed within the first opening, and a second insulating layer is applied over the first insulating layer and formed with a plurality of second openings, wherein the metal layer within the first opening is exposed via at least one second opening. After a conductive layer is applied over the second insulating layer and within the second openings, a metal layer is formed within the second openings. Finally, the conductive layer is removed by micro-etching.