Abstract: In a wireless communication system, a method and system for implementing an FI function in a KASUMI algorithm for accelerating cryptography in GSM/GPRS/EDGE compliant handsets are provided. An efficient implementation of the FI function may comprise a first substitution stage and a second substitution stage, where a 9-bit substitution circuit and a 7-bit substitution circuit may be used in each of the stages. A pipe register may be used to transfer and zero-extend an input to the 7-bit substitution circuit for processing with an output of the 9-bit substitution circuit. A first multiplexer and a second multiplexer may be used to select the inputs for the substitution circuits at each one of the substitution stages. A third multiplexer and a fourth multiplexer may be used to select subkeys for encryption during the first substitution stage and zero value signals during the second substitution stage.

Abstract: In a wireless communication system, a method and system for implementing a KASUMI algorithm for accelerating cryptography in GSM/GPRS/EDGE compliant handsets are provided. A pipelined implementation of the KASUMI algorithm may comprise a plurality of selectors, an FI function, an FO function, a first pipe register, a second pipe register, and an XOR operation. A selected first portion of the input data may be transferred to the first pipe register and a selected second portion to the second pipe register. A first output may be generated based on the transferred second portion of the input data while the transferred first portion of the input data may correspond to a second output. A plurality of control signals may control the inputs to the FO function and to the FL function according to whether the round of processing is an even round or an odd round.

Abstract: In a wireless communication system, a method and system for implementing an FO function in a KASUMI algorithm for accelerating cryptography in GSM/GPRS/EDGE compliant handsets are provided. An efficient implementation of the FO function may comprise circuitry provided for a pipeline state machine, an FI function, a controller, a pipe register, and an XOR operation. Signals may be generated to control each round of FI processing and to indicate when each round is complete. The pipeline state machine may provide data input and subkey to the FI function for processing. A first and a second round FI processing outputs may be transferred to the pipe register. The second round output may be clocked from the pipe register to generate a portion of the FO function output and may also be XORed with a third round output of FI processing to generate the remaining portion of the FO function output.

Abstract: A video processor within a wireless terminal, that includes a video interface that receives incoming video information and that provides outgoing video information, a processing module operably coupled to the video interface, and a video accelerator module and a motion processing processor accelerator operably coupled to the processing module. The processing of the incoming video information and the outgoing video information is performed by the combination of the processing module, processor accelerator and the video accelerator module. Compute intensive operations may be offloaded from the processing module onto the video accelerator to improve overall system efficiency.

Abstract: A video processor within a wireless terminal, that includes a video interface that receives incoming video information and that provides outgoing video information, a processing module operably coupled to the video interface, and a video accelerator module and a motion processing co-processor operably coupled to the processing module. The processing of the incoming video information and the outgoing video information is performed by the combination of the processing module, co-processor and the video accelerator module. Compute intensive operations may be offloaded from the processing module onto the video accelerator to improve overall system efficiency.