Abstract: Due to the test current and the test temperature of the wafer-level reliability depend on each other in those conventional arts, the result of electromigration etc is not sure cause of the test current or the test temperature and debases the reliability of the test result. In the present invention, the electromigration test and the stress migration test of the wafer-level reliability are independently controlled, respectively. Therefore, the cause of electromigration and the stress migration can be sure resulting from the test current or the test temperature respectively. Furthermore, the isothermal heater of the present invention not only can keep a whole test wafer at a more uniform test temperature, but also can offset the electromagnetism resulted from the current of the isothermal heater by the arrangement of circuits thereof for reducing the effect of the electromagnetism.

Abstract: A bonding pad structure formed on a semiconductor substrate comprises an insulating layer, a conducting pad, a passivation layer, and a buffer layer. The insulating layer is formed on the semiconductor substrate. The conducting pad is formed on the insulating layer, and the passivation layer is formed to cover peripherals of the conducting pad forming an overhang region therebetween. However, the buffer layer is patterned and etched to form a plurality of either islands or openings between the insulating layer and the conducting pad but withon the range of the overhang region. Accordingly, peeling resistance ability can be enhanced via a form of mechanical interlocking. In addition, a portion of the overhang region can be wider than the other portion thereof in order to further intensify the adhesion between the conducting pad and the passivation layer.

Abstract: A bonding pad structure in accordance with the present invention is formed on a semiconductor substrate. The bonding pad structure comprises a buffer layer, a planarization layer, a conducting pad, and a passivation layer. The buffer layer is formed over the semiconductor substrate, and the planarization layer is thereafter formed on the buffer layer. The buffer layer is patterned and etched to shape a plurality of contact holes. The conducting pad is formed on the planarization layer and filled in the contact holes in order to mechanically interlock with the planarization layer. The passivation layer overlies peripherals of the conducting pad forming an overhang region therebetween. Moreover, the width of a portion of the overhang region close to a drawing direction may be enlarged so that the adhesion between the conducting pad and the passivation layer can be increased.