Patents by Inventor Ruggero Castagnetti
Ruggero Castagnetti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140253226Abstract: An apparatus having one or more of a plurality of circuits in a first level of a hierarchy and two or more of the circuits in a second level of the hierarchy is disclosed. The circuits are configured to (i) allocate a profile from the first level down to the second level, (ii) manage from the second level a respective power consumed by each of a plurality of blocks based on the profile and (iii) maintain a sum of the powers approximately constant by increasing the power consumed by a first of the blocks while decreasing the power consumed by a second of the blocks.Type: ApplicationFiled: March 13, 2013Publication date: September 11, 2014Applicant: LSI CORPORATIONInventors: Ting Zhou, Ruggero Castagnetti, Chris Sonnek
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Publication number: 20140169113Abstract: A memory system and a memory repair method for the memory system are disclosed. The method includes the steps of: organizing at least one repair block to serve as a shared repair resource for the plurality of memory blocks in the tiled memory; identifying a defective memory unit among the plurality of memory blocks in the tiled memory; identifying a replacement unit in the repair block for replacement of the defective memory unit; retrieving a set of memory blocks from the plurality of memory blocks in the tiled memory in response to a data access request, wherein the set of memory blocks retrieved containing the defective memory unit; retrieving the replacement unit from the repair block in response to the data access request; and replacing the defective memory unit in the set of memory blocks with the replacement unit.Type: ApplicationFiled: June 5, 2013Publication date: June 19, 2014Inventors: Ting Zhou, Ross A. Kohler, Ruggero Castagnetti, Michael G. Yee, Concetta Riccobene
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Patent number: 8738940Abstract: A rush-in current controller includes a clock module connected to provide a delayed sleep control signal based on counting a preset number of clock cycles corresponding to an input sleep control signal. Additionally, the rush-in current controller includes a ring oscillator module connected to maintain the delayed sleep control signal based on counting a preset number of ring oscillator cycles corresponding to a virtual power supply line voltage. A method of controlling a rush-in current includes providing a delayed sleep control signal based on counting a preset number of clock cycles corresponding to an input sleep control signal and maintaining the delayed sleep control signal based on counting a preset number of ring oscillator cycles corresponding to a virtual power supply line voltage.Type: GrantFiled: September 6, 2011Date of Patent: May 27, 2014Assignee: LSI CorporationInventors: Ramnath Venkatraman, Shashidhara S. Bapat, Ruggero Castagnetti
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Publication number: 20140040842Abstract: A method of reducing total power dissipation for logic cells using Boolean equations includes selecting a path, identifying at least one group of logic cells for analysis in the path, and deriving Boolean equations for the at least one group of logic cells. Additionally, the method includes listing possible logic cell implementations for each Boolean equation while maintaining original transistor values, verifying path timing for the possible logic cell implementations to provide retained logic cells that achieve a path timing requirement, computing a total power dissipation for the retained logic cells, and choosing a logic cell set from the retained logic cells corresponding to a minimum total power dissipation for the path. A method for reducing total power dissipation for logic cell sets and a processor configured to reduce total power dissipation for groups of logic cells are also provided.Type: ApplicationFiled: October 14, 2013Publication date: February 6, 2014Applicant: LSI CorporationInventors: Benjamin Mbouombouo, Ramnath Venkatraman, Ruggero Castagnetti
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Publication number: 20140028364Abstract: A critical path monitor (CPM), a method of setting supply voltage based on output of a CPM and an integrated circuit (IC) incorporating the CPM. In one embodiment, the CPM includes: (1) an edge detector configured to produce a thermometer output over a plurality of clock cycles and (2) a min_max recorder, coupled to the edge detector and configured to record minimum and maximum values of the thermometer output during a polling interval.Type: ApplicationFiled: July 27, 2012Publication date: January 30, 2014Applicant: LSI CorporationInventors: Ramnath Venkatraman, Prasad Subbarao, Ruggero Castagnetti
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Patent number: 8589853Abstract: A method of reducing total power dissipation for logic cells includes selecting a distribution of logic cells corresponding to at least one path, computing a dynamic to static power ratio for each logic cell in the distribution of logic cells and ranking the dynamic to static power ratio for each logic cell into a lower group, a middle group and an upper group of logic cells. Additionally, the method includes swapping the lower group of logic cells and the upper group of logic cells for a reconfigured middle group of logic cells and verifying path timing for the reconfigured middle group of logic cells. Methods of reducing total power dissipation using Boolean equations and for logic cell sets are also provided.Type: GrantFiled: May 9, 2011Date of Patent: November 19, 2013Assignee: LSI CorporationInventors: Benjamin Mbouombouo, Ramnath Venkatraman, Ruggero Castagnetti
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Publication number: 20130166931Abstract: Described embodiments provide for a memory system which power-gates a memory operating at a first clock. Control logic in the memory system activates, during a rising edge of a second clock, the memory from a sleep mode. The memory is accessed. After a cycle of the first clock, the control logic asserts a power-gating signal, thereby returning the memory to the sleep mode. The frequency of the second clock is less than a frequency of the first clock.Type: ApplicationFiled: December 23, 2011Publication date: June 27, 2013Inventors: Ruggero Castagnetti, Ting Zhou, Ramnath Venkatraman
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Publication number: 20130166930Abstract: Described embodiments provide for a memory system adapted to enable power-gating in one or more memories. Each memory has a corresponding timing characteristic. A monitor in the memory system determines a timing threshold and determines whether the timing characteristic of a memory is at least equal to the timing threshold. If the corresponding timing characteristic is at least equal to the timing threshold, power-gating is applied to the memory.Type: ApplicationFiled: December 23, 2011Publication date: June 27, 2013Inventors: Ting Zhou, Ruggero Castagnetti, Ramnath Venkatraman
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Patent number: 8411399Abstract: An integrated circuit power supply decoupling circuit includes a capacitor and a protection circuit. The capacitor has a first terminal and a second terminal. The protection circuit includes a first transistor having a first conduction path, and a second transistor having a second conduction path. One terminal of the first conduction path is connected to the first terminal of the capacitor, and another terminal of the first conduction path is connected to a first power supply rail. One terminal of the second conduction path is connected to the second terminal of the capacitor, and another terminal of the second conduction path is connected to a second power supply rail.Type: GrantFiled: July 19, 2010Date of Patent: April 2, 2013Assignee: LSI CorporationInventors: Ramnath Venkatraman, Ruggero Castagnetti
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Publication number: 20130057338Abstract: A rush-in current controller includes a clock module connected to provide a delayed sleep control signal based on counting a preset number of clock cycles corresponding to an input sleep control signal. Additionally, the rush-in current controller includes a ring oscillator module connected to maintain the delayed sleep control signal based on counting a preset number of ring oscillator cycles corresponding to a virtual power supply line voltage. A method of controlling a rush-in current includes providing a delayed sleep control signal based on counting a preset number of clock cycles corresponding to an input sleep control signal and maintaining the delayed sleep control signal based on counting a preset number of ring oscillator cycles corresponding to a virtual power supply line voltage.Type: ApplicationFiled: September 6, 2011Publication date: March 7, 2013Applicant: LSI CorporationInventors: Ramnath Venkatraman, Shashidhara S. Bapat, Ruggero Castagnetti
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Publication number: 20120290994Abstract: A method of reducing total power dissipation for logic cells includes selecting a distribution of logic cells corresponding to at least one path, computing a dynamic to static power ratio for each logic cell in the distribution of logic cells and ranking the dynamic to static power ratio for each logic cell into a lower group, a middle group and an upper group of logic cells. Additionally, the method includes swapping the lower group of logic cells and the upper group of logic cells for a reconfigured middle group of logic cells and verifying path timing for the reconfigured middle group of logic cells. Methods of reducing total power dissipation using Boolean equations and for logic cell sets are also provided.Type: ApplicationFiled: May 9, 2011Publication date: November 15, 2012Applicant: LSI CorporationInventors: Benjamin Mbouombouo, Ramnath Venkatraman, Ruggero Castagnetti
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Patent number: 8112734Abstract: A method incorporating adaptive body biasing into an integrated circuit design flow includes the steps of (A) adding adaptive body biasing input/outputs (I/Os) during a bonding layout stage of the integrated circuit design flow, (B) floorplanning the integrated circuit design, (C) generating an adaptive body biasing mesh and (D) generating a layout of the integrated circuit design based upon a plurality of adaptive body biasing corners.Type: GrantFiled: September 29, 2008Date of Patent: February 7, 2012Assignee: LSI CorporationInventors: Benjamin Mbouombouo, Ramnath Venkatraman, Ruggero Castagnetti
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Publication number: 20110051304Abstract: An integrated circuit power supply decoupling circuit includes a capacitor and a protection circuit. The capacitor has a first terminal and a second terminal. The protection circuit includes a first transistor having a first conduction path, and a second transistor having a second conduction path. One terminal of the first conduction path is connected to the first terminal of the capacitor, and another terminal of the first conduction path is connected to a first power supply rail. One terminal of the second conduction path is connected to the second terminal of the capacitor, and another terminal of the second conduction path is connected to a second power supply rail.Type: ApplicationFiled: July 19, 2010Publication date: March 3, 2011Applicant: LSI CorporationInventors: Ramnath Venkatraman, Ruggero Castagnetti
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Patent number: 7869251Abstract: Disclosed is a method and device for providing fast-response One-Time-Programmable (OTP) memory based on SRAM memory technology and the inherent breakdown characteristics of a MOS transistor. Each memory cell of an SRAM memory cell circuit is connected to a programming circuit. The programming circuit is comprised of two groups of MOS transistors connected to the storage nodes (SN and SNB, where SNB is the complementary value of SN) of the two cross-coupled inverters of the SRAM memory circuit. A desired data set is loaded into the circuit and then is burned-in by applying and repeatedly cycling a “burn-in” voltage across the source and drain of the MOS transistors of the programming circuit that approaches the ON STATE trigger voltage of the characteristic bipolar junction transistor contained within the MOS transistors.Type: GrantFiled: September 26, 2008Date of Patent: January 11, 2011Assignee: LSI CorporationInventors: Ramnath Venkatraman, Ruggero Castagnetti, Subramanian Ramesh
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Publication number: 20100080035Abstract: Disclosed is a method and device for providing fast-response One-Time-Programmable (OTP) memory based on SRAM memory technology and the inherent breakdown characteristics of a MOS transistor. Each memory cell of an SRAM memory cell circuit is connected to a programming circuit. The programming circuit is comprised of two groups of MOS transistors connected to the storage nodes (SN and SNB, where SNB is the complementary value of SN) of the two cross-coupled inverters of the SRAM memory circuit. A desired data set is loaded into the circuit and then is burned-in by applying and repeatedly cycling a “burn-in” voltage across the source and drain of the MOS transistors of the programming circuit that approaches the ON STATE trigger voltage of the characteristic bipolar junction transistor contained within the MOS transistors.Type: ApplicationFiled: September 26, 2008Publication date: April 1, 2010Inventors: Ramnath Venkatraman, Ruggero Castagnetti, Subramanian Ramesh
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Publication number: 20100083193Abstract: A method incorporating adaptive body biasing into an integrated circuit design flow includes the steps of (A) adding adaptive body biasing input/outputs (I/Os) during a bonding layout stage of the integrated circuit design flow, (B) floorplanning the integrated circuit design, (C) generating an adaptive body biasing mesh and (D) generating a layout of the integrated circuit design based upon a plurality of adaptive body biasing corners.Type: ApplicationFiled: September 29, 2008Publication date: April 1, 2010Inventors: Benjamin Mbouombouo, Ramnath Venkatraman, Ruggero Castagnetti
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Patent number: 7440356Abstract: The present invention provides a system and method for designing and modularly expanding multiport bitcells. A modular design approach is described that reduces the complexity of designing multiport bitcells while complying with DFM rules across various semiconductor fabrication providers. The modular design may be parsed into modules such as read port modules, write port modules, and pull-up modules that may be easily interconnected to build a multiport bitcell. These modules may also be independently sized and assembled to achieve desired read margins, write margins, static noise margins as well as read access times and write times.Type: GrantFiled: July 13, 2006Date of Patent: October 21, 2008Assignee: LSI CorporationInventors: Ramnath Venkatraman, Ruggero Castagnetti, Subramanian Ramesh
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Publication number: 20080013383Abstract: The present invention provides a system and method for designing and modularly expanding multiport bitcells. A modular design approach is described that reduces the complexity of designing multiport bitcells while complying with DFM rules across various semiconductor fabrication providers. The modular design may be parsed into modules such as read port modules, write port modules, and pull-up modules that may be easily interconnected to build a multiport bitcell. These modules may also be independently sized and assembled to achieve desired read margins, write margins, static noise margins as well as read access times and write times.Type: ApplicationFiled: July 13, 2006Publication date: January 17, 2008Inventors: Ramnath Venkatraman, Ruggero Castagnetti, Subramanian Ramesh
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Patent number: 7304874Abstract: Improved layouts of binary and ternary content addressable memory cells (BCAM and TCAM) are shown. A content addressable memory cell layout has a plurality of P+ diffusion areas and a plurality of N+ diffusion areas that do not enclose isolation regions and on which shallow trench isolation stress can exert minimal influence on the drive current of the memories. Further, all transistors in the content addressable memory cell layout are oriented in the same direction to avoid unintended variations in electrical performance. The CAM layouts are “process friendly” to accommodate requirements of advanced process technologies such as the 90 nm process.Type: GrantFiled: March 8, 2005Date of Patent: December 4, 2007Assignee: LSI CorporationInventors: Ramnath Venkatraman, Ruggero Castagnetti, Joseph Eugene Glenn
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Publication number: 20060203530Abstract: Improved layouts of binary and ternary content addressable memory cells (BCAM and TCAM) are shown. A content addressable memory cell layout has a plurality of P+ diffusion areas and a plurality of N+ diffusion areas that do not enclose isolation regions and on which shallow trench isolation stress can exert minimal influence on the drive current of the memories. Further, all transistors in the content addressable memory cell layout are oriented in the same direction to avoid unintended variations in electrical performance. The CAM layouts are “process friendly” to accommodate requirements of advanced process technologies such as the 90 nm process.Type: ApplicationFiled: March 8, 2005Publication date: September 14, 2006Inventors: Ramnath Venkatraman, Ruggero Castagnetti, Joseph Glenn