Patents by Inventor Rui Chen

Rui Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250147969
    Abstract: Provided are a data processing method and a data processing apparatus based on a user profile, a device, a medium, and a program. The method includes: acquiring multiple pieces of user data and a generation time of a last piece of user data; generating, each time a piece of first user data is read from the pieces of user data, a user feature corresponding to the first user data; storing the user feature corresponding to the first user data into a target database when a generation time of the first user data is consistent with the generation time of the last piece of user data; otherwise, not storing the user feature corresponding to the first user data into the target database; and generating a user profile based on the user feature in the target database.
    Type: Application
    Filed: January 8, 2025
    Publication date: May 8, 2025
    Inventors: Rui CHEN, Shujun WANG, Tao YANG, Hongli GE, Xiaoyong PENG
  • Publication number: 20250151298
    Abstract: A method of manufacturing a semiconductor structure includes forming on a substrate, at intervals in a first direction, a first trench, a second trench, and a third trench, forming a first oxide layer in the first trench, forming a second oxide layer in the second trench, and forming a third oxide layer in the third trench. The method also includes forming a first semiconductor material layer in the first trench, forming a second semiconductor material layer in the second trench, and forming a third semiconductor material layer in the third trench. The method further includes forming a mask layer, performing a first etching process on the mask layer to form a first opening and a second opening, performing a second etching process at the second opening to form a third surface on the substrate, and forming a first doped region adjacent to the third surface exposed by the second opening.
    Type: Application
    Filed: October 30, 2024
    Publication date: May 8, 2025
    Applicant: Diodes Incorporated
    Inventors: Tao Long, Ze Rui Chen, Pin-Hao Huang, Bau-Shun Huang, Lee Spencer Riley
  • Patent number: 12287448
    Abstract: A five-point deconvolution method for quantification of uranium ores by energy spectrum logging disclosed by the invention refers to: carry out ? spectrum logging along the borehole to obtain logging curves in multiple energy zones, using these logging curves and energy spectrum features, inversion calculate the distribution of uranium content along the borehole; the main features are: first, realize the subdivision interpretation of layered strata; second, realize multi-element stripping for energy spectrum logging; third, realize subdivision interpretation by the five-point deconvolution methods; fourth, on-site uranium ores quantification under fast spectral logging conditions can be realized; the invention also discloses two types of algorithm flows of “first stripping, then subdividing” and “first subdividing, then stripping” and the formula for solving the uranium/thorium/potassium content of the unit layer.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: April 29, 2025
    Inventors: Bin Tang, Xiongjie Zhang, Haitao Wang, Zhifeng Liu, Yan Zhang, Renbo Wang, Lijiao Zhang, Rui Chen, Fan Huang, Shumin Zhou, Jinhui Qu
  • Publication number: 20250130444
    Abstract: Spatial light modulators and associated methods are described. In one embodiment, a spatial light modulator includes a photonic integrated circuit configured for emitting a plurality of light beams as a first waveform by a plurality of pixels. The light beams are individually controllable. The spatial light modulator also includes a meta-optic having a plurality of nanostructures configured for receiving the first waveform and aggregating the plurality of light beams as a second waveform at a surface of the meta-optic. The spatial light modulator also includes an aperture array configured for converting the second waveform into a third waveform, where the third waveform is smaller than the second waveform.
    Type: Application
    Filed: July 30, 2024
    Publication date: April 24, 2025
    Applicant: UNIVERSITY OF WASHINGTON
    Inventors: Virat Tara, Anna-Wirth Singh, Abhi Saxena, Johannes Emanuel Fröch, Matthew S. Reynolds, Rui Chen, Arka Majumdar
  • Patent number: 12278631
    Abstract: A main board, a hot plug control signal generator, and a control signal generating method thereof are provided. The hot plug control signal generator includes a controller and a latch. The controller provides a control signal. The latch is operated based on an operation power to generate a hot plug control signal. The latch sets the hot plug control signal to a disabled first logic value, and latches the hot plug control signal at the first logic value.
    Type: Grant
    Filed: May 29, 2024
    Date of Patent: April 15, 2025
    Assignee: Wiwynn Corporation
    Inventors: Wei-Fang Chang, Yu-Chun Chen, Nan-Huan Lin, Chung-Hui Yen, Shi-Rui Chen
  • Patent number: 12270070
    Abstract: The invention is a novel method of generating a library of circular single stranded nucleic acid molecules by utilizing circular capture molecules. The method is not limited by size of target nucleic acid molecules and can potentially accommodate very long molecules. The method finds application in nucleic acid sequencing, e.g., nanopore sequencing where unlimited-length templates can be read.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: April 8, 2025
    Assignee: Roche Sequencing Solutions, Inc.
    Inventors: Rui Chen, Toumy Guettouche, Aaron Richardson
  • Patent number: 12269189
    Abstract: A concentric-ring single-sided dovetail groove ceramic tile back mold core is disclosed. A vulcanized rubber of back mold core surface comprises raised patterns and recessed patterns integrally formed, pasted and covered on a back mold core iron substrate. The raised patterns are equidistantly offset outwards layer by layer with a central position of the back mold core as a center; and a side of each raised pattern close to the center is of an equiangular obtuse angle, and a side of each raised pattern far away from the center is of an acute angle with an angular equal difference gradually decreasing.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: April 8, 2025
    Inventors: Rui Chen, Guo Chen
  • Publication number: 20250098057
    Abstract: The embodiment of the present disclosure provides a method for generating an extreme ultraviolet light, an extreme ultraviolet light source assembly, and an optical system. The method for generating an extreme ultraviolet light includes: generating a plasma by using a magnetic confinement device; controlling, if the plasma meets a preset injection condition, a heavy metal injection device to inject a designated heavy metal into the magnetic confinement device, so that the designated heavy metal interacts with the plasma in the magnetic confinement device to generate an extreme ultraviolet light; controlling an optical device to collect the extreme ultraviolet light.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 20, 2025
    Applicant: Shaanxi Startorus Fusion Technology Company Limited
    Inventors: Yi Tan, Rui Chen
  • Patent number: 12251823
    Abstract: Various embodiments relate to magnetically moveable displacement devices or robotic devices. Particular embodiments provide systems and corresponding methods for magnetically moving multiple movable robots relative to one or more working surfaces of respective one or more work bodies, and for moving robots between the one or more work bodies via transfer devices. Robots can carry one or more objects among different locations, manipulate carried objects, and/or interact with their surroundings for particular functionality including but not limited to assembly, packaging, inspection, 3D printing, test, laboratory automation, etc. A mechanical link may be mounted on planar motion units such as said robots.
    Type: Grant
    Filed: June 2, 2023
    Date of Patent: March 18, 2025
    Assignee: Planar Motor Incorporated
    Inventors: Xiaodong Lu, Peter Tang, Alexander H. Slocum, Rui Chen
  • Publication number: 20250072030
    Abstract: A device includes a substrate, a semiconductor layer and a ferroelectric layer. The semiconductor layer is over the substrate. The semiconductor layer is a single crystal silicon layer or a single crystal germanium layer. The ferroelectric layer is over the semiconductor layer. The ferroelectric layer is in physical contact with the semiconductor layer and has an orthorhombic phase.
    Type: Application
    Filed: August 23, 2023
    Publication date: February 27, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., National Yang Ming Chiao Tung University
    Inventors: Yu-Rui CHEN, Zefu ZHAO, Yun-Wen CHEN, Chee-Wee LIU
  • Patent number: 12222641
    Abstract: The present disclosure provides a method for optimizing mask parameters, and the method includes: acquiring a test pattern, light source parameters, and initial mask parameters, the initial mask parameters including a mask thickness and an initial mask sidewall angle; generating multiple sets of candidate mask parameters according to the initial mask sidewall angle in the initial mask parameters; the multiple sets of candidate mask parameters including different mask sidewall angles and the same mask thickness; obtaining an imaging contrast of each set of candidate mask parameters based on the test pattern and the light source parameters; and selecting an optimal mask sidewall angle from the multiple sets of candidate mask parameters according to the imaging contrasts.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: February 11, 2025
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Jianfang He, Yayi Wei, Yajuan Su, Lisong Dong, Libin Zhang, Rui Chen, Le Ma
  • Patent number: 12218256
    Abstract: A semiconductor structure includes: a substrate, having a cell region and a terminal region, and having a first surface, a second located in the terminal region, and a third surface located in the cell region, the second surface and the third surface being located at different levels; a first trench structure, located in the cell region, traversing the third surface to extend towards the first surface, including a first semiconductor material layer and a first oxide layer partially protruding from the third surface, and extending in a first direction parallel to the third surface; and a second trench structure, located in the cell region, including a second semiconductor material layer and a second oxide layer partially protruding from the third surface, and extending parallel to the first direction, wherein the third surface is provided with a doped region between the first trench structure and the second trench structure.
    Type: Grant
    Filed: July 16, 2024
    Date of Patent: February 4, 2025
    Assignee: DIODES INCORPORATED
    Inventors: Tao Long, Ze Rui Chen, Pin-Hao Huang, Bau-Shun Huang, Lee Spencer Riley
  • Publication number: 20250040226
    Abstract: The present disclosure provides a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device includes: a substrate; an insulating layer provided with a plurality of trenches extending in a first direction; a first electrode layer and a second electrode layer, where a spacing region is provided between the first electrode layer and the second electrode layer; a semiconductor layer covering bottom portions and sidewalls of all channel trenches, where the channel trenches are at least a part of trench bodies of the trenches located in the spacing region; a gate dielectric layer covering a surface of the semiconductor layer in the channel trenches on a side away from the bottom portions and the sidewalls of the channel trenches; a gate layer, where at least a part of the channel trenches are fully filled with the gate layer.
    Type: Application
    Filed: July 26, 2024
    Publication date: January 30, 2025
    Inventors: Junjie LI, Gaobo Xu, Na Zhou, Chenchen Zhang, Jianfeng Gao, Yihong Lu, Tao Yang, Junfeng Li, Jun Luo, Rui Chen
  • Publication number: 20250033661
    Abstract: This document describes trajectory planning in a three-dimensional (3D) search space with a space-time artificial potential field. An example system includes a processor that obtains an initial pose, a goal pose, and an obstacle map for an environment. The processor uses a parking trajectory algorithm to determine a trajectory by searching in a space-time artificial potential field. The trajectory includes a series of 3D waypoints, including two-dimensional (2D) positional coordinates and time coordinates, to navigate from the initial pose towards the goal pose. Operation of the host vehicle is then controlled to maneuver along the trajectory using an assisted-driving or autonomous-driving system. In this way, path searching is performed in the entire 3D search space rather than iterating between two 2D search planes. This allows motion planning for autonomous parking, especially with static and dynamic objects present, to determine an optimal trajectory in a single iteration.
    Type: Application
    Filed: July 26, 2023
    Publication date: January 30, 2025
    Inventors: Qian Wang, Rui Chen
  • Publication number: 20250033109
    Abstract: A method of manufacturing a metal braided net includes arranging a plurality of wires to form a plurality of pairs of wires contiguous to each other. An intertwining step is proceeded to intertwine each pair of wires a predetermined number of turns to form an intertwining portion. A displacement step is proceeded to make each pair of wires displace relative to each other through a predetermined distance. After an end of each of the plurality of wires has formed an inclining portion, plural pairs of contiguous metal wires are formed. The intertwining and displacement steps are repeated to form a metal braided net having hexagonal meshes and a predetermined size. Then, a bending portion is formed on each of the plurality of wires and protrudes outward from at least one of an upper and a lower surfaces of the metal braided net. A metal braided net is also disclosed.
    Type: Application
    Filed: July 25, 2023
    Publication date: January 30, 2025
    Inventors: CHUNG-PING CHEN, PO-RUI CHEN
  • Patent number: 12199192
    Abstract: A semiconductor rectifier device includes: an epitaxial layer, having a top surface and a bottom surface; a first doped region having a first conductivity type, located in the epitaxial layer; a first trench structure, located in the first doped region; a second trench structure adjacent to the first trench structure, located in the first doped region; a second doped region having a second conductivity type, located in the epitaxial layer between the first trench structure and the second trench structure, wherein a depth of the second doped region is less than a depth of the first trench structure; and a metal layer, located on the top surface of the epitaxial layer, covering the first trench structure, the second trench structure, and the second doped region, wherein the metal layer is in contact with the top surface, forming a Schottky interface.
    Type: Grant
    Filed: January 17, 2024
    Date of Patent: January 14, 2025
    Assignee: Diodes Incorporated
    Inventors: Tao Long, Ze Rui Chen, Pin-Hao Huang, Bau-Shun Huang
  • Patent number: 12197598
    Abstract: Systems and methods for enabling cross-tenant access are provided. In particular, a computing device may receive an access request, from a user of a first tenant, requesting access to a resource of a plurality of resources on a shared collaborative channel of a second tenant. The computing device may further evaluate cross-tenant access policies of the first and second tenants to determine that access to the plurality of resources is authorized by the first and second tenants, validate that the user is a member of the shared collaborative channel, and generate a validation token indicating the user is validated to access the plurality of resources. Based on the validation token, the computing device may further validate that the user is in compliance with the cross-tenant access policies for accessing the resource and grant the user a set of permissions to access the resource.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: January 14, 2025
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Michael Thomas McLean, Ladislau Conceicao, Glenn David Block, Timothy Yu-Rui Chen, Dean Shiyu Chiang, Matthias Leibmann
  • Publication number: 20250010246
    Abstract: The present disclosure relates to an apparatus and a method for filtration. The apparatus for filtration may include at least one filtration layer and at least one flow-through layer disposed along a filtration direction of the filtration layer. One of the at least one flow-through layer may include at least one first support member and at least one first flow channel. The at least one first flow channel may be configured for a liquid to flow, and the at least one first support member may define the at least one first flow channel.
    Type: Application
    Filed: July 8, 2024
    Publication date: January 9, 2025
    Applicant: ALIT BIOTECH (SHANGHAI) CO., LTD.
    Inventors: Guoqian XU, Rui CHEN
  • Publication number: 20250015199
    Abstract: A semiconductor rectifier device comprises: an epitaxial layer having a top surface and a bottom surface; a first trench comprising a first side wall, a second side wall, and a first bottom surface; a second trench adjacent to the first trench, the second trench comprising a third side wall, a fourth side wall, and a second bottom surface; a first doped region abutting against the first side wall and at least a part of the first bottom surface of the first trench; a second doped region adjacent to and separated from the first doped region, wherein the second doped region abuts against the third side wall, the fourth side wall and the second bottom surface of the second trench; a gate structure disposed on the top surface between the first trench and the second trench; and a contact metal layer disposed on the top surface of the epitaxial layer.
    Type: Application
    Filed: July 18, 2024
    Publication date: January 9, 2025
    Applicant: Diodes Incorporated
    Inventors: Tao Long, Ze Rui Chen, Pin-Hao Huang, Paul Keith Gurry, Li-Hsien Chou
  • Patent number: D1071985
    Type: Grant
    Filed: January 18, 2023
    Date of Patent: April 22, 2025
    Inventor: Rui Chen