Abstract: A display substrate and a display device are disclosed. The display substrate includes a base substrate and a plurality of shift register units; each of the plurality of shift register units includes an input circuit, an output circuit, a first reset circuit and a frame reset signal connection wire; the frame reset signal connection wire and is configured to provide a frame reset signal to the first reset circuit; the first reset circuit is configured to respond to the frame reset signal, so as to reset a first node and an output end within a time period between two display frames of the display substrate; the first reset circuit includes a first transistor and a second transistor, and the frame reset signal connection wire, a gate of the first transistor and a gate of the second transistor are provided on a first conductive layer.

Abstract: Disclosed are a gate driving circuit and a display device. According to the gate driving circuit, in every five adjacent shift registers, the output control end of the first shift register is electrically connected to the input signal end of the fifth shift register; in every six adjacent shift registers, the output control end of the sixth shift register is electrically connected to the reset signal end of the first shift register.

Abstract: A display substrate and a display device are disclosed. The display substrate includes a base substrate and a plurality of shift register units; each of the plurality of shift register units includes an input circuit, an output circuit, a first reset circuit and a frame reset signal connection wire; the frame reset signal connection wire and is configured to provide a frame reset signal to the first reset circuit; the first reset circuit is configured to respond to the frame reset signal, so as to reset a first node and an output end within a time period between two display frames of the display substrate; the first reset circuit includes a first transistor and a second transistor, and the frame reset signal connection wire, a gate of the first transistor and a gate of the second transistor are provided on a first conductive layer.

Abstract: A shift register includes an input sub-circuit, a first noise reduction sub-circuit, and a first pull-down sub-circuit. The first noise reduction sub-circuit is coupled to the pull-up node, the first pull-down node and a first voltage signal terminal, and is configured to transmit a first voltage signal to the pull-up node under control of the first pull-down node; the input sub-circuit is coupled to the pull-up node and a signal input terminal, and is configured to transmit an input signal to the pull-up node in response to the input signal; the first pull-down sub-circuit is coupled to the signal input terminal, the first pull-down node and the first voltage signal terminal, and is configured to transmit the first voltage signal to the first pull-down node in response to the input signal, so that the first noise reduction sub-circuit stops transmitting the first voltage signal to the pull-up node.

Abstract: The present disclosure provides a GOA circuit, an array substrate and a display device, wherein the GOA circuit comprises: a GOA area, and the GOA area comprises a plurality of GOA unit circuits cascaded with each other; a lead area, wherein at least one STV signal line and at least one non-STV signal line are arranged in the lead area, each STV signal line and each non-STV signal line is connected to at least one GOA unit circuit, and the non-STV signal line comprises at least one of a Vdd signal line, a Clk signal line, a VGH signal line and a VGL signal line; a projection of the at least one STV signal line on the lead area does not overlap a projection of the at least one non-STV signal line on the lead area.

Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a common electrode. The common electrode includes an electrode unit array. The electrode unit array includes a plurality of electrode units. Each of the electrode units corresponds to two adjacent sub-pixels. Each of the electrode units includes a boundary electrode line and an inner region defined by the boundary electrode line. The inner region includes a first region and a second region. The first region includes a plurality of first strip electrode lines having a same longitudinal direction. Two adjacent first strip electrode lines are not connected inside the first region. The second region includes a plurality of second strip electrode lines having a same longitudinal direction. Two adjacent second strip electrode lines are not connected inside the second region.

Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a common electrode. The common electrode includes an electrode unit array. The electrode unit array includes a plurality of electrode units. Each of the electrode units corresponds to two adjacent sub-pixels. Each of the electrode units includes a boundary electrode line and an inner region defined by the boundary electrode line. The inner region includes a first region and a second region. The first region includes a plurality of first strip electrode lines having a same longitudinal direction. Two adjacent first strip electrode lines are not connected inside the first region. The second region includes a plurality of second strip electrode lines having a same longitudinal direction. Two adjacent second strip electrode lines are not connected inside the second region.

Abstract: A display substrate and a display device are disclosed. The display substrate includes a base substrate and a plurality of shift register units; each of the plurality of shift register units includes an input circuit, an output circuit, a first reset circuit and a frame reset signal connection wire; the frame reset signal connection wire and is configured to provide a frame reset signal to the first reset circuit; the first reset circuit is configured to respond to the frame reset signal, so as to reset a first node and an output end within a time period between two display frames of the display substrate; the first reset circuit includes a first transistor and a second transistor, and the frame reset signal connection wire, a gate of the first transistor and a gate of the second transistor are provided on a first conductive layer.

Abstract: A shift register includes an input sub-circuit, a first noise reduction sub-circuit, and a first pull-down sub-circuit. The first noise reduction sub-circuit is coupled to the pull-up node, the first pull-down node and a first voltage signal terminal, and is configured to transmit a first voltage signal to the pull-up node under control of the first pull-down node; the input sub-circuit is coupled to the pull-up node and a signal input terminal, and is configured to transmit an input signal to the pull-up node in response to the input signal; the first pull-down sub-circuit is coupled to the signal input terminal, the first pull-down node and the first voltage signal terminal, and is configured to transmit the first voltage signal to the first pull-down node in response to the input signal, so that the first noise reduction sub-circuit stops transmitting the first voltage signal to the pull-up node.

Abstract: Disclosed are a gate driving circuit and a display device. According to the gate driving circuit, in every five adjacent shift registers, the output control end of the first shift register is electrically connected to the input signal end of the fifth shift register; in every six adjacent shift registers, the output control end of the sixth shift register is electrically connected to the reset signal end of the first shift register.

Abstract: The present disclosure relates to a display substrate, a method for driving the same, and a display panel. The display substrate includes a base substrate as well as gate lines, data lines and a gate driver on the base substrate, the gate line being connected to the gate driver, and electrostatic rings and control components corresponding to at least one gate line are further disposed on the base substrate, each of the gate lines being connected to the electrostatic ring by a corresponding control component. The electrostatic ring is configured to load a control voltage to turn on the corresponding control component after the display panel is turned off, and the corresponding control component is configured to be turned on to change a voltage on the gate line into a turn-on voltage after the display panel is turned off.

Abstract: A display device and driving method thereof and a manufacturing method of a display substrate involve an array substrate and manufacturing method thereof. The array substrate includes: a base substrate; and a number of display sub-pixels arranged in a matrix on the base substrate. Each individual display sub-pixel includes: a pixel electrode; a first common electrode; and a second common electrode; wherein the first common electrode and the second common electrode are insulated from each other; and wherein the pixel electrode is configured to interact respectively with the first common electrode and the second common electrode so as to conduct one or more display operations.

Abstract: Embodiments of the present disclosure provide a shift register, a gate driving circuit, and a display apparatus. The shift register comprises a power consumption-reducing sub-circuit and an output sub-circuit; wherein: the power consumption-reducing sub-circuit is connected to a clock signal terminal, a control terminal, and the output sub-circuit, the power consumption-reducing sub-circuit is used to output a signal of the clock signal terminal to the output sub-circuit under the control of the control terminal; the output sub-circuit is connected to the clock signal terminal through the power consumption-reducing sub-circuit and is also connected to an output terminal and a pull-up node, the output sub-circuit is used to output an output signal of the power consumption-reducing sub-circuit to the output terminal under the control of the pull-up node.

Abstract: A display substrate includes an active area; and a gate-driver-on-array (GOA) circuit area, wherein the active area includes a display pixel area and a dummy pixel area located in the periphery of the display pixel area, and wherein the GOA circuit area includes at least one dummy GOA circuit having an output terminal connected to a pixel electrode of at least one dummy pixel.

Abstract: The present disclosure provides a drift control circuit, a drift control method, a gate driving unit, a gate driving method and a display device. The drift control circuit includes: a first drift control sub-circuit configured to, during noise releasing performed by the first pull-down module, control first electrodes of pull-down transistors included in the second pull-down module to be coupled to a first control voltage terminal, which is configured to input a first voltage to the first pull-down module during noise releasing performed by the first pull-down module; and a second drift control sub-circuit configured to, during noise releasing performed by the second pull-down module, control first electrodes of pull-down transistors included in the first pull-down module to be coupled to a second control voltage terminal, which is configured to input the first voltage to the second pull-down module during noise releasing performed by the second pull-down module.

Abstract: The present disclosure provides a GOA circuit, an array substrate and a display device, wherein the GOA circuit comprises: a GOA area, and the GOA area comprises a plurality of GOA unit circuits cascaded with each other; a lead area, wherein at least one STV signal line and at least one non-STV signal line are arranged in the lead area, each STV signal line and each non-STV signal line is connected to at least one GOA unit circuit, and the non-STV signal line comprises at least one of a Vdd signal line, a Clk signal line, a VGH signal line and a VGL signal line; a projection of the at least one STV signal line on the lead area does not overlap a projection of the at least one non-STV signal line on the lead area.

Abstract: The present application discloses a gate-driving unit circuit. The gate-driving unit circuit includes an input sub-circuit coupled to an input terminal and a pull-up node, and configured to charge a pull-up node to a turn-on voltage level. Additionally, the gate-driving unit circuit includes a pre-pull-down sub-circuit coupled to a pull-down node, a pre-pull-down node, and a reference voltage terminal, and configured to pull down voltage levels at the pull-down node and the pre-pull-down node to a turn-off voltage level before the pull-up node is charged to the turn-on voltage level. Therefore, potential charging delay in the pull-down node caused by a transistor threshold voltage shift is avoided. The gate-driving unit circuit further includes a pull-down sub-circuit, a pull-down control sub-circuit, a noise-reduction sub-circuit, a reset sub-circuit, and an output sub-circuit to couple with the input sub-circuit and the pre-pull-down sub-circuit to output a gate-driving signal.

Abstract: A liquid crystal display device and a drive method thereof are disclosed. The liquid crystal display device includes a display panel and a controller. The display panel includes a display region, a plurality of pixels arranged in a matrix are provided in the display region, each of the plurality of pixels includes a red sub-pixel, a blue sub-pixel and a green sub-pixel, and the display region includes a middle portion and a peripheral portion outside the middle portion, and at least one first pixel is provided in the peripheral portion, the controller is configured to relatively increase a luminous intensity of a blue sub-pixel in the first pixel.

Abstract: A display device and driving method thereof and a manufacturing method of a display substrate involve an array substrate and manufacturing method thereof. The array substrate includes: a base substrate; and a number of display sub-pixels arranged in a matrix on the base substrate. Each individual display sub-pixel includes: a pixel electrode; a first common electrode; and a second common electrode; wherein the first common electrode and the second common electrode are insulated from each other; and wherein the pixel electrode is configured to interact respectively with the first common electrode and the second common electrode so as to conduct one or more display operations.

Abstract: The present application discloses a gate-driving unit circuit. The gate-driving unit circuit includes an input sub-circuit coupled to an input terminal and a pull-up node, and configured to charge a pull-up node to a turn-on voltage level. Additionally, the gate-driving unit circuit includes a pre-pull-down sub-circuit coupled to a pull-down node, a pre-pull-down node, and a reference voltage terminal, and configured to pull down voltage levels at the pull-down node and the pre-pull-down node to a turn-off voltage level before the pull-up node is charged to the turn-on voltage level. Therefore, potential charging delay in the pull-down node caused by a transistor threshold voltage shift is avoided. The gate-driving unit circuit further includes a pull-down sub-circuit, a pull-down control sub-circuit, a noise-reduction sub-circuit, a reset sub-circuit, and an output sub-circuit to couple with the input sub-circuit and the pre-pull-down sub-circuit to output a gate-driving signal.