Abstract: Provided are an audio/video processing method and apparatus, a device, and a storage medium. The method comprises: displaying text data corresponding to an audio/video to be edited, wherein the text data has a mapping relation with an audio/video timestamp of said audio/video; displaying said audio/video according to a time axis track; in response to a preset operation triggered for target text data in the text data, determining an audio/video timestamp corresponding to the target text data as a target audio/video timestamp; and processing, on the basis of the preset operation, an audio/video clip corresponding to the target audio/video timestamp in said audio/video.

Abstract: The present disclosure relates to the technical field of genetic engineering, in particular to a target ligand. The target ligand provided by the present disclosure forms a siRNA conjugate with a specific small interfering RNA sequence, which targets to an angiopoietin like 3 (ANGPTL3), and reduce the expression quantity of an ANGPTL3 protein by degrading a transcript of an ANGPTL3 gene in a cell. Therefore, the siRNA conjugate formed by the target ligand provided by the present disclosure may be used to prevent and/or treat a dyslipidemia disease.

Abstract: An electronic device includes a substrate, a transistor, and a ring resonator. The transistor is over the substrate. The ring resonator is over the substrate and overlaps with the transistor. The ring resonator includes a conductive loop and an impedance matching element. The conductive loop includes a loop portion having two first parts and a second part and two feeding lines. Each of the first parts of the loop portion is between the second part of the loop portion and one of the feeding lines, and a tunnel barrier of the transistor is closer to the second part than to the feeding lines. The impedance matching element is closer to the feeding lines than to the second part.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit on a semiconductor substrate. First and second gate electrode structures are disposed over the substrate and are spaced laterally from one another. A common source/drain region is disposed in the semiconductor substrate between the first and second gate electrode structures. An insulator layer overlies the first and second gate electrode structures. A source/drain contact extends through the insulator layer between the first and second gate electrode structures to contact the common source/drain region. First and second sidewall spacer structures are disposed along outer sidewalls of the first and second gate electrode structures, respectively, and have first and second outer sidewalls, respectively, adjacent to the source/drain contact.

Abstract: Provided are compounds and salts having a structure of Formula (I) or (II): (I), and (II) wherein: both of the chiral carbon atoms denoted by “*” are both in the R configuration or both in the S configuration. Compounds and salts of Formulae (I) and (II) are useful in the preparation of enantiomerically pure amino acids. Conversion of amino acids to D-form from any of L-form, racemate or other enantiomerically impure mixtures or conversion of amino acids to L-form from any of D-form, racemate or other enantiomerically impure mixtures is disclosed.

Abstract: Provided is an intelligent analysis system for inner detecting magnetic flux leakage (MFL) data in pipelines, including a complete data set building module, a discovery module, a quantization module and a solution module, wherein: a complete data set building method is adopted in the complete data set building module to obtain a complete magnetic flux leakage data set; a pipeline connecting component discovery method is adopted in the discovery module to obtain the precise position of a weld; an anomaly candidate region search and identification method is adopted in the discovery model to find out magnetic flux leakage signals with defects; a defect quantization method based on a random forest is adopted in the quantization module to obtain a defect size; and a pipeline solution based on an improved ASME B31G standard is adopted in the solution module to output an evaluation result.

Abstract: An electronic device includes a substrate, a transistor, and a ring resonator. The transistor is over the substrate. The ring resonator is over the substrate and includes a conductive loop and an impedance matching element. The conductive loop overlaps with the transistor. The impedance matching element is on the conductive loop and electrically isolated from the transistor.

Abstract: An electronic device includes a substrate, a transistor, and a ring resonator. The transistor is over the substrate. The transistor is configured to generate a quantum dot. The ring resonator is over the substrate and includes a conductive loop and an impedance matching element. The conductive loop overlaps with the transistor. The impedance matching element is on the conductive loop and is configured to determine a resonance frequency of the ring resonator.

Abstract: An electronic device includes a substrate, a transistor, and a ring resonator. The transistor is over the substrate. The transistor is configured to generate a quantum dot. The ring resonator is over the substrate and includes a conductive loop and an impedance matching element. The conductive loop overlaps with the transistor. The impedance matching element is on the conductive loop and is configured to determine a resonance frequency of the ring resonator.

Abstract: Provided is an intelligent analysis system for inner detecting magnetic flux leakage (MFL) data in pipelines, including a complete data set building module, a discovery module, a quantization module and a solution module, wherein: a complete data set building method is adopted in the complete data set building module to obtain a complete magnetic flux leakage data set; a pipeline connecting component discovery method is adopted in the discovery module to obtain the precise position of a weld; an anomaly candidate region search and identification method is adopted in the discovery model to find out magnetic flux leakage signals with defects; a defect quantization method based on a random forest is adopted in the quantization module to obtain a defect size; and a pipeline solution based on an improved ASME B31G standard is adopted in the solution module to output an evaluation result.

Abstract: A permeable cement stone fracturing exploitation method for non-conventional oil and gas layer comprising the following processes: transporting and storing a supercritical carbon dioxide to a well site; selecting, transporting, and storing an oil well cement and admixtures to the well site; mixing the oil well cement and the admixtures into a first mixture, forming a cement slurry; pumping the supercritical carbon dioxide and the cement slurry respectively into a high pressure mixer; automatically mixing the supercritical carbon dioxide and the cement slurry into a second mixture by the high pressure mixer; continuously on-line monitoring and temporarily storing the second mixture; and injecting the second mixture into the non-conventional oil and gas layer for fracturing to form a reticulate artificial fracture; the second mixture is automatically heated, pressure reduced, gasified, solidified, carbonic acid dissolved and eroded, leached to form the a permeable cement stone.

Abstract: Disclosed is a permeable cement stone fracturing exploitation method for non-conventional oil and gas layer such as tight oil and gas, shale gas, coal-bed gas, combustible ice and so on. The method comprises the following complementary processes and embodiments: transporting, storing and pumping process for supercritical carbon dioxide; transporting, storing, preparing and pumping process for fracturing cement slurry; process for mixing the supercritical carbon dioxide and the cement slurry; process of fracturing the supercritical carbon dioxide and the cement slurry on ground; process of forming a permeable cement stone under the ground; and so on.

Abstract: A liquid crystal display (LCD) device with a driving method includes an LCD panel, a data driving circuit, a common voltage generating circuit, and a gate driving circuit. The LCD panel includes multiple data lines and multiple scanning lines intersecting with the data lines, and a common electrode. The gate driving circuit provides multiple gate-scanning signals to scan the scanning lines. The common voltage generating circuit provides a common voltage to the common electrode. The data driving circuit provides a gray level voltage signal including multiple voltage levels to the data lines. The common voltage is serial square waves having at least two non-identical frame periods. The square waves in each non-identical frame period of the common voltage in one frame have a constant period.

Abstract: A liquid crystal display (LCD) device with a driving method includes an LCD panel, a data driving circuit, a common voltage generating circuit, and a gate driving circuit. The LCD panel includes multiple data lines and multiple scanning lines intersecting with the data lines, and a common electrode. The gate driving circuit provides multiple gate-scanning signals to scan the scanning lines. The common voltage generating circuit provides a common voltage to the common electrode. The data driving circuit provides a gray level voltage signal including multiple voltage levels to the data lines. The common voltage is serial square waves having at least two non-identical frame periods. The square waves in each non-identical frame period of the common voltage in one frame have a constant period.

Abstract: Calling a linear access window at a predetermined fixed address allows accessing of a data block in an on-chip memory of a microprocessor. Hardware concatenation of a page number held in a start address register with an indicated offset produces the needed complete address without the need of an adder. In the process, the hardware checks that the indicated address falls within a predetermined address space. If the address exceeds the predetermined address space, during concatenation the hardware substitutes the lowest page number in the predetermined address space for the current page number in the start address register, effectively wrapping the address space without the need for software checking and intervention.

Abstract: A network switcher for data transfer between a network communication unit and a plurality of nodes is provided. In this network switcher, the interface ports or MAC (media access control) addresses are divided into groups, and the data transfer is permitted only between those interface ports or MAC addresses within the same group. This feature can avoid a node-information signal whose destination address is not yet acknowledged to be transferred to all of the other interface ports beside the destination one. Conventionally, this drawback significantly degrades the performance of the overall network system. This network switcher allows an improvement on the performance of network systems that has a number of nodes.

Abstract: A method and apparatus for storing data and searching in the address table of an Ethernet switch device. The Ethernet switch device includes a central switch and a number of device port connectors which each have a port, a router, an address table, and a media access controller. The router includes a destination address register and a multiplexer. The destination address register receives network addressing information from the media access controller and divides it into a number of address sections. The multiplexer receives the address sections from the register for successively multiplexing the sections into multiplexed address outputs. The multiplexed address outputs are compared with entries stored in the address table to find a match with address information contained in the entries. The central switch connects to the port of the device port connector identified by a port number contained in the network addressing information corresponding to the match.

Abstract: A run length encoder for converting bi-level video image data made up of white and black representative pixel values to a run length code to be used by a vector processor including a transition detector for detecting the transition of inputted image data values from either white to black or black to white. The inputted image data are addressed along each scanned line. At every white to black transition, the pixel address is stored in memory. The number of continuous black pixels following this first transition is counted until a black to white transition is detected. The resulting count value corresponding to each stored address value for each black "run" is also stored in memory, wherein these stored values represent the run length code of the video image data for use with the vector processor.