Abstract: The present application relates to the technical field of data processing, and discloses a data processing method and apparatus, a device, and a medium. The method comprises: based on a bus address space allocated for a first slave device, writing data to be processed into a storage component of the first slave device through a first peripheral component interconnect express link, in order that the first slave device processes the data to be processed and obtains result data; obtaining the result data sent by the first slave device; and determining a destination address of the result data, and in response to that the destination address points to a storage space of a second slave device, writing the result data into a storage component of the second slave device through a second peripheral component interconnect express link. The problems of high communication delay and high hardware resource overhead during data transmission exist in the prior art.

Abstract: A compound of formula (I) or a pharmaceutically acceptable salt, an enantiomer, a diastereomer, a solvate, a hydrate, a polymorph or an isotopic variant thereof, which can promote binding of butyrophilin 3A1/2A1, wherein the definitions of groups are as detailed in the description and the claims. Also involved are a pharmaceutical composition containing the compound of formula (I) and use thereof in clinical treatment.

Abstract: A compound of formula (I) or a pharmaceutically acceptable salt, enantiomer, diastereoisomer, solvate, hydrate, polymorph or an isotopic variant thereof. The compound can promote the binding of butyrophilin 3A1/2A1, and the definition of each group in formula (I) is as detailed in the description and the claims. The present invention further relates to a pharmaceutical composition containing the compound of formula (I) and the use thereof in clinical treatments.

Abstract: A server system and a communication method of a server system are provided. The server system includes: at least one first processor board and a host server; the first processor board includes a first field programmable gate array chip and a first processor chip, the first field programmable gate array chip and the first processor chip being packaged and interconnected; the host server is configured to transmit host data to the first field programmable gate array chip through the switching network; and the first field programmable gate array chip is configured to process the host data, receive request data sent by the first processor chip, generate a communication protocol message according to processed host data and the request data, and transmit the communication protocol message to a target processor board through the switching network.

Abstract: A display substrate includes a substrate and a display region, an isolation region, a peripheral region and a hole disposed on the substrate, wherein the display region surrounds the hole, the isolation region is disposed between the display region and the peripheral region, and the peripheral region surrounds and adjoins the hole; the isolation region is provided with an isolation column and a first inorganic structure, the isolation column is disposed at a side of the substrate, and the first inorganic structure is disposed at a side of the isolation column away from the substrate; and the peripheral region is provided with a structure layer, and the structure layer is disposed on the substrate and includes a first organic structure and a second inorganic structure disposed along a direction perpendicular to the substrate; wherein the first inorganic structure, the second inorganic structure and the first organic structure all are made of an insulation material, and the first inorganic structure and the sec

Abstract: A server, a method for executing a task and apparatus, and a non-transitory readable storage medium is provided. The server includes a processor, a processor memory, and an accelerator connected to the processor. The accelerator includes an accelerator memory. The address spaces of the processor memory and the accelerator memory are addressed uniformly based on a CXL protocol to obtain a unified memory. The processor can acquire original data of a target task, store the original data into the unified memory, write instruction data into a register of the accelerator based on the target task; the accelerator can generate an instruction based on the instruction data written into the register, acquire the original data from the unified memory based on the CXL protocol, execute the instruction based on the original data to complete the target task, and write the task execution result into the unified memory.

Abstract: The present application discloses a method and apparatus of direct memory access DMA between accelerator cards, an accelerator card, an accelerating platform and a non-volatile readable storage medium in the technical field of computers. The first accelerator card according to the present application can initiatively perform the initiation of the DMA, and, according to the idle-internal-memory datum of the second accelerator card as the data destination terminal recorded in the first accelerator card itself, write the datum directly into the internal memory of the second accelerator card in the mode of DMA, which does not require inquiring the idle-internal-memory address of the second accelerator card before the DMA, and does not require waiting for the second accelerator card to initiate the DMA. The solution realizes the direct DMA writing operation between different accelerator cards at the hardware level, and solves the problem in DMA operation between accelerator cards.

Abstract: A method and apparatus of direct memory access DMA between accelerator cards, an accelerator card, an accelerating platform and a non-volatile readable storage medium. The first accelerator card according to the present application can initiatively perform the initiation of the DMA, and, according to the idle-internal-memory datum of the second accelerator card as the data destination terminal recorded in the first accelerator card itself, write the datum directly into the internal memory of the second accelerator card in the mode of DMA, which does not require inquiring the idle-internal-memory address of the second accelerator card before the DMA, and does not require waiting for the second accelerator card to initiate the DMA. The solution realizes the direct DMA writing operation between different accelerator cards at the hardware level, and solves the problem in DMA operation between accelerator cards.

Abstract: The present application discloses a data processing system and method, and a medium in the technical field of model training. According to the present application, a model training task is executed using acceleration devices in a host; and train data, intermediate results and weight data are stored using a memory board in the host, whereby the host does not need to execute the task or store the data.

Abstract: The present disclosure provides a method for communication between nodes. The method includes: obtaining a list of field-programmable gate arrays; virtualizing the field-programmable gate arrays according to the list of field-programmable gate arrays to obtain a first source node and a first target node; obtaining an application descriptor between the first source node and the first target node, the application descriptor includes a memory address of the first source node and a memory address of the first target node; obtaining an identity document of the first source node according to the memory address, and obtaining an identity document of the first target node according to the memory address; and performing a communication action on the first source node and the first target node through a remote direct memory access module according to the identity document of the first source node and the identity document of the first target node.

Abstract: The present disclosure provides a method for communication between nodes. The method includes: obtaining a list of field-programmable gate arrays; virtualizing the field-programmable gate arrays according to the list of field-programmable gate arrays to obtain a first source node and a first target node; obtaining an application descriptor between the first source node and the first target node, the application descriptor includes a memory address of the first source node and a memory address of the first target node; obtaining an identity document of the first source node according to the memory address, and obtaining an identity document of the first target node according to the memory address; and performing a communication action on the first source node and the first target node through a remote direct memory access module according to the identity document of the first source node and the identity document of the first target node.

Abstract: Provided are a communication method and system for a distributed heterogeneous acceleration platform, a device and a medium. The method includes: after starting a collaborative acceleration task, determining, by a first target heterogeneous acceleration card in a distributed heterogeneous acceleration platform, a second target heterogeneous acceleration card from the distributed heterogeneous acceleration platform by querying an information table corresponding to the collaborative acceleration task; generating, by the first target heterogeneous acceleration card, a target data packet according to a predefined data packet format, and sending the target data packet to the second target heterogeneous acceleration card via a PCIE interface; and parsing, by the second target heterogeneous acceleration card, the target data packet according to the data packet format, and executing a corresponding read operation or write operation according to a parsing result, so as to complete the collaborative acceleration task.

Abstract: A display substrate is provided, including: a base substrate including at least pixel and hole areas; sub-pixels arranged on the base substrate and in the pixel area; a hole in the hole area; a first barrier dam between the sub-pixels and the hole and at least partially surrounding the hole; a functional film layer, an organic material layer and an encapsulating structure sequentially arranged on the display substrate in a direction away from the base substrate, an orthographic projection of the organic material layer on the base substrate falling within the pixel area, the organic material layer including at least one film layer; and a filling structure, at least a portion of which is arranged between the hole and the first barrier dam. The filling structure and the at least one film layer of the organic material layer are in the same layer and include the same material.

Abstract: Provided is a micro- and nano-fluidic chip, including at least one nanochannel array layer and at least one microchannel array layer that are alternately stacked. The at least one nanochannel array layer includes nanochannels, the at least one microchannel array layer includes input units and/or output units. The input unit includes inlet microchannel arrays and inlets, and the output unit includes outlet microchannel arrays and outlets. The inlet microchannel array includes inlet microchannels, the outlet microchannel array includes outlet microchannels, and the inlet microchannels and the outlet microchannels are connected through the nanochannels.

Abstract: Provided is a micro- and nano-fluidic chip, including at least one nanochannel array layer and at least one microchannel array layer that are alternately stacked. The at least one nanochannel array layer includes nanochannels, the at least one microchannel array layer includes input units and/or output units. The input unit includes inlet microchannel arrays and inlets, and the output unit includes outlet microchannel arrays and outlets. The inlet microchannel array includes inlet microchannels, the outlet microchannel array includes outlet microchannels, and the inlet microchannels and the outlet microchannels are connected through the nanochannels.

Abstract: The present disclosure relates to data processing, and in particular, to a system for processing a full-stack network card task based on FPGA. The system includes: a network interface controller, configured to receive to-be-processed data, and offload a TCP/IP task from the to-be-processed data by a built-in TCP offload engine, to obtain first processed data; an SSL/TLS protocol processing module, configured to receive the first processed data, and offload an SSL/TLS protocol task from the first processed data, to obtain second processed data; a PR region, configured to receive the second processed data; and a reconfiguration module, configured to acquire, by a host, dynamic configuration information of the PR region, and configure the PR region based on the dynamic configuration information, so that the PR region offloads and processes computation-intensive tasks in the second processed data.

Abstract: The present disclosure relates to data processing, and in particular, to a system for processing a full-stack network card task based on FPGA. The system includes: a network interface controller, configured to receive to-be-processed data, and offload a TCP/IP task from the to-be-processed data by a built-in TCP offload engine, to obtain first processed data; an SSL/TLS protocol processing module, configured to receive the first processed data, and offload an SSL/TLS protocol task from the first processed data, to obtain second processed data; a PR region, configured to receive the second processed data; and a reconfiguration module, configured to acquire, by a host, dynamic configuration information of the PR region, and configure the PR region based on the dynamic configuration information, so that the PR region offloads and processes computation-intensive tasks in the second processed data.

Abstract: A compound as represented by formula I or a pharmaceutically acceptable form thereof, a pharmaceutical composition containing same, and the medical use thereof for preventing and/or treating HPK1-related diseases.

Abstract: Provided are a communication method and system for a distributed heterogeneous acceleration platform, a device and a medium. The method includes: after starting a collaborative acceleration task, determining, by a first target heterogeneous acceleration card in a distributed heterogeneous acceleration platform, a second target heterogeneous acceleration card from the distributed heterogeneous acceleration platform by querying an information table corresponding to the collaborative acceleration task; generating, by the first target heterogeneous acceleration card, a target data packet according to a predefined data packet format, and sending the target data packet to the second target heterogeneous acceleration card via a PCIE interface; and parsing, by the second target heterogeneous acceleration card, the target data packet according to the data packet format, and executing a corresponding read operation or write operation according to a parsing result, so as to complete the collaborative acceleration task.

Abstract: A display substrate is provided, including: a base substrate including at least pixel and hole areas; sub-pixels arranged on the base substrate and in the pixel area; a hole in the hole area; a first barrier dam between the sub-pixels and the hole and at least partially surrounding the hole; a functional film layer, an organic material layer and an encapsulating structure sequentially arranged on the display substrate in a direction away from the base substrate, an orthographic projection of the organic material layer on the base substrate falling within the pixel area, the organic material layer including at least one film layer; and a filling structure, at least a portion of which is arranged between the hole and the first barrier dam. The filling structure and the at least one film layer of the organic material layer are in the same layer and include the same material.