Abstract: Provided is a method for transmitting image data. The method includes acquiring initial image data of a to-be-displayed image in a display panel, wherein the display panel includes a plurality of pixels, and the initial image data includes pixel data of the plurality of pixels; compressing pixel data of a plurality of first pixels in the initial image data to acquire at least one piece of compressed pixel data, wherein the plurality of first pixels are disposed in a non-foveal region of the display panel, and a plurality of second pixels are disposed in a foveal region of the display panel; sending compressed image data to a driver chip of the display panel, wherein the compressed image data comprises the at least one piece of compressed pixel data and pixel data of the plurality of second pixels.

Abstract: A configuration for reporting OOD samples for neural network optimization. The apparatus receives, from a base station, a configuration to report an OOD dataset for a machine learning model. The apparatus detects an occurrence of one or more OOD events. The apparatus reports the OOD dataset comprising the one or more OOD events based on the configuration to report OOD dataset. The apparatus receives, from the base station, an update to the machine learning model. The OOD dataset may comprise raw data related to the one or more OOD events, or may comprise extracted latent data corresponding to features of raw data related to the one or more OOD events.

Abstract: The present disclosure discloses a degassing-free underwater dissolved carbon dioxide detection device and a detection method. The degassing-free underwater dissolved carbon dioxide detection device includes a computer, which is used to provide the driving signal and controlling parameters for the power tuning unit; the computer is connected with a laser driving control module and the power tuning unit, respectively; the laser driving control module is connected with a laser; the laser is connected with a photo-isolator; the photo-isolator is connected with a thulium-doped fiber vertical-cavity laser system; the thulium-doped fiber vertical-cavity laser system is connected with a photoacoustic cell system through a fiber collimator; the photoacoustic cell system is connected with a pre-amplifier circuit and a lock-in amplifier in sequence, and the lock-in amplifier is connected with the computer.

Abstract: Provided is a preparation method of a detector material. The present disclosure epitaxially grows a buffer layer on a surface of a gallium arsenide substrate, deposits a silicon dioxide layer on the buffer layer, and etches the silicon dioxide layer on the buffer layer according to a strip pattern by photolithography and etching to form strip growth regions with continuous changes in width. Finally, a molecular beam epitaxy (MBE) technology is used to epitaxially grow the detector material in the strip growth regions under set epitaxy growth conditions. Because of the same mobility of atoms arriving at the surface of the substrate, numbers of atoms migrating to the strip growth regions are different due to different widths of the strip growth regions, such that compositions of the material change with the widths of the strip growth regions or a layer thickness changes with the widths of the strip growth regions.

Abstract: A method, system and apparatus for the sharing of an FPGA board by multiple virtual machines. Specifically, in the present application, a PCIE virtual layer (comprising a plurality of PCIE virtual sub-layers) and a virtual PCIE device are created; one virtual machine corresponds to one virtual PCIE device, multiple virtual PCIE devices correspond to one PCIE virtual sub-layer, and one PCIE virtual sub-layer corresponds to one FPGA board, thus enabling multiple virtual machines to share and use the FPGA board through one PCIE virtual sub-layer (that is, the multiple virtual machines share one PCIE bus, and same all access the FPGA board through the PCIE bus), thereby solving the problem of some of the virtual machines being unable to be started at the same time, and enhancing the experience effect of a user.

Abstract: Processes, catalysts and systems for preparing a composition comprising aliphatic, olefinic, cyclic and/or aromatic hydrocarbons of seven or greater carbon atoms per molecule are provided.

Abstract: A far-end data migration device and method based on a FPGA cloud platform. The device includes a server, a switch, and a plurality of FPGA acceleration cards. The server transmits data to be accelerated to the FPGA acceleration cards by means of the switch. The FPGA acceleration cards are configured to perform a primary and/or secondary acceleration on the data, and are configured to migrate the accelerated data. The method includes: transmitting data to be accelerated to a FPGA acceleration card from a server by means of a switch; performing, by the FPGA acceleration card, a primary and/or secondary acceleration on the data to be accelerated; and migrating, by the FPGA acceleration card, the accelerated data.

Abstract: A field-programmable gate array (FPGA)-based FAST protocol decoding method, apparatus, and device, and a readable storage medium. The method acquires an actual XML template in real time and analyzes the actual XML template, generates a FAST protocol intermediate representation, and determines, according to preset decoding parameters, the maximum number of fields which are read at a single time, so as to generate a field matching state machine. Thus, the present disclosure can support a dynamically updated XML template, and allows flexible setting of the maximum number of fields according to an actual network bandwidth, and is applicable to disclosure scenarios of different network bandwidths. In a decoding process, the present disclosure realizes, by means of a field shift register and the field matching state machine, the function of reading and decoding a plurality of fields in parallel each time, significantly improving decoding efficiency.

Abstract: An information recording method, apparatus, and device, and a readable storage medium are provided. The method includes: when a server is started, determining a ring buffer in a Double Data Rate (DDR) of a Field-Programmable Gate Array (FPGA) acceleration card based on an OpenPower platform; determining a start address and an end address of the ring buffer and configuring the start address and the end address to the FPGA acceleration card; and during a running process of the server, recording preset debugging information to the ring buffer in real time, so as to perform fault location according to data in the ring buffer after a fault occurs in the server. According to the present application, during a running process of a server, preset debugging information is recorded using a DDR of an FPGA acceleration card; therefore, when a down fault causes a Central Processing Unit (CPU) error of a server, recording of debugging information can also be ensured, thereby facilitating fault location.

Abstract: The method includes: an FPGA board feeds back the quantity of controllers and the total quantity of DDR memories after receiving a hardware information acquisition request from a host; after a data space application request is received from the host, on the basis of the data space application request, perform data slice processing on data to be calculated, wherein the data space application request carries the dedicated application space capacity of each DDR and the data to be calculated, and the total quantity of slices of the data to be calculated is the same as the total quantity of DDR memories; and transmit each sliced data to a corresponding DDR space, and according to a data storage position of the sliced data in each DDR, read the data from the DDR memory space in parallel by means of the plurality of controllers and calculate same.

Abstract: The method includes: an FPGA board feeds back the quantity of controllers and the total quantity of DDR memories after receiving a hardware information acquisition request from a host; after a data space application request is received from the host, on the basis of the data space application request, perform data slice processing on data to be calculated, wherein the data space application request carries the dedicated application space capacity of each DDR and the data to be calculated, and the total quantity of slices of the data to be calculated is the same as the total quantity of DDR memories; and transmit each sliced data to a corresponding DDR space, and according to a data storage position of the sliced data in each DDR, read the data from the DDR memory space in parallel by means of the plurality of controllers and calculate same.

Abstract: A display substrate includes a substrate and a display region, an isolation region, a peripheral region and a hole disposed on the substrate, wherein the display region surrounds the hole, the isolation region is disposed between the display region and the peripheral region, and the peripheral region surrounds and adjoins the hole; the isolation region is provided with an isolation column and a first inorganic structure, the isolation column is disposed at a side of the substrate, and the first inorganic structure is disposed at a side of the isolation column away from the substrate; and the peripheral region is provided with a structure layer, and the structure layer is disposed on the substrate and includes a first organic structure and a second inorganic structure disposed along a direction perpendicular to the substrate; wherein the first inorganic structure, the second inorganic structure and the first organic structure all are made of an insulation material, and the first inorganic structure and the sec

Abstract: In one aspect, antibodies that specifically bind to a human alpha-synuclein protein are provided. In some embodiments, an anti-alpha-synuclein antibody binds to monomeric human alpha-synuclein protein, oligomeric human alpha-synuclein protein, soluble human alpha-synuclein protein, human alpha-synuclein protein fibrils, and human alpha-synuclein protein that is phosphorylated at Ser129 (pSer129) with high affinity. In some embodiments, an anti-alpha-synuclein antibody can specifically bind to or immunodeplete alpha-synuclein protein. In some embodiments, an anti-alpha-synuclein antibody can prevent or inhibit alpha-synuclein seeding.

Abstract: A far-end data migration device and method based on a FPGA cloud platform. The device includes a server, a switch, and a plurality of FPGA acceleration cards. The server transmits data to be accelerated to the FPGA acceleration cards by means of the switch. The FPGA acceleration cards are configured to perform a primary and/or secondary acceleration on the data, and are configured to migrate the accelerated data. The method includes: transmitting data to be accelerated to a FPGA acceleration card from a server by means of a switch; performing, by the FPGA acceleration card, a primary and/or secondary acceleration on the data to be accelerated; and migrating, by the FPGA acceleration card, the accelerated data.

Abstract: A display substrate, a manufacturing method thereof, and a display device are provided. The display substrate includes: a base substrate at least including a pixel area and a hole area; a plurality of sub-pixels arranged on the base substrate and located in the pixel area; a hole in the hole area; a first barrier dam arranged between the sub-pixels and the hole and at least partially surrounding the hole; an organic material layer including at least one film layer, wherein an orthographic projection of the organic material layer on the base substrate falls within the pixel area; and a filling structure, wherein at least a portion of the filling structure is arranged between the hole and the first barrier dam, and the filling structure and the at least one film layer of the organic material layer are located in the same layer and include the same material.

Abstract: Provided is a micro- and nano-fluidic chip, including at least one nanochannel array layer and at least one microchannel array layer that are alternately stacked. The at least one nanochannel array layer includes nanochannels, the at least one microchannel array layer includes input units and/or output units. The input unit includes inlet microchannel arrays and inlets, and the output unit includes outlet microchannel arrays and outlets. The inlet microchannel array includes inlet microchannels, the outlet microchannel array includes outlet microchannels, and the inlet microchannels and the outlet microchannels are connected through the nanochannels.

Abstract: Provided are a data processing method and device based on a convolutional neural network. For any convolutional layer in a convolutional neural network, calculation is performed by a convolution kernel of the convolutional layer, on elements of data inputted to the convolutional layer one by one so as to obtain convoluted values of the respective elements. Each calculation obtains a convoluted value, and this convoluted value and convoluted values of elements in the same region obtained by calculation through the same convolution kernel are added together to obtain an output element of the convolution kernel corresponding to the region. In this way, an output of a convolutional layer can be obtained after all convoluted values have been calculated without having to read convoluted values from a storage apparatus, thus enhancing data processing efficiency.

Abstract: A method, system and apparatus for the sharing of an FPGA board by multiple virtual machines. Specifically, in the present application, a PCIE virtual layer (comprising a plurality of PCIE virtual sub-layers) and a virtual PCIE device are created; one virtual machine corresponds to one virtual PCIE device, multiple virtual PCIE devices correspond to one PCIE virtual sub-layer, and one PCIE virtual sub-layer corresponds to one FPGA board, thus enabling multiple virtual machines to share and use the FPGA board through one PCIE virtual sub-layer (that is, the multiple virtual machines share one PCIE bus, and same all access the FPGA board through the PCIE bus), thereby solving the problem of some of the virtual machines being unable to be started at the same time, and enhancing the experience effect of a user.

Abstract: An electronic device and a housing for the electronic device are provided. The housing includes a metal part. The metal part includes at least one spiral slot formed on the metal part A portion of the metal part which is disposed between an innermost loop and an outermost loop of the spiral slot forms a spiral metal coil by being spaced by the spiral slot. The spiral metal coil is configured as an antenna radiation element electrically connected with an antenna circuit inside the electronic device, and the spiral slot is filled with an insulating material.

Abstract: In one aspect, antibodies that specifically bind to a human triggering receptor expressed on myeloid cells 2 (TREM2) protein are provided. In some embodiments, the antibody increases levels of soluble TREM2 (sTREM2). In some embodiments, the antibody decreases levels of sTREM2. In some embodiments, the antibody enhances TREM2 activity. In some embodiments, the antibody inhibits TREM2 activity.