Patents by Inventor Rui Ito

Rui Ito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250183782
    Abstract: A power supply circuit has a first node, a second node, a DC-DC converter that includes a switched capacitor, generates an output voltage based on an input voltage supplied from the first node, and outputs the output voltage from the second node, and a regulator that is connected in parallel to the DC-DC converter between the first node and the second node and controls an output current flowing to the second node based on a reference voltage lower than the input voltage.
    Type: Application
    Filed: February 6, 2025
    Publication date: June 5, 2025
    Applicant: Kioxia Corporation
    Inventors: Makoto MORIMOTO, Rui ITO, Ryuichi FUJIMOTO
  • Patent number: 12244217
    Abstract: A power supply circuit has a first node, a second node, a DC-DC converter that includes a switched capacitor, generates an output voltage based on an input voltage supplied from the first node, and outputs the output voltage from the second node, and a regulator that is connected in parallel to the DC-DC converter between the first node and the second node and controls an output current flowing to the second node based on a reference voltage lower than the input voltage.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: March 4, 2025
    Assignee: Kioxia Corporation
    Inventors: Makoto Morimoto, Rui Ito, Ryuichi Fujimoto
  • Publication number: 20220302817
    Abstract: A power supply circuit has a first node, a second node, a DC-DC converter that includes a switched capacitor, generates an output voltage based on an input voltage supplied from the first node, and outputs the output voltage from the second node, and a regulator that is connected in parallel to the DC-DC converter between the first node and the second node and controls an output current flowing to the second node based on a reference voltage lower than the input voltage.
    Type: Application
    Filed: September 15, 2021
    Publication date: September 22, 2022
    Inventors: Makoto MORIMOTO, Rui ITO, Ryuichi FUJIMOTO
  • Patent number: 11183230
    Abstract: According to one embodiment, a sense amplifier circuit includes an amplifier having an input terminal connected to a sense node, and a first capacitor configured to be connected in a feedback path of the amplification transistor and to a bit line of a memory cell via the sense node, the first capacitor configured to supply a current to the memory cell and integrate the current when the memory cell is read.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: November 23, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Rui Ito, Takeshi Hioka, Takuyo Kodama
  • Patent number: 11100975
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of memory cells connected to a word line, a circuit configured to apply a voltage to the word line, a detection circuit configured to detect a first time difference from when a first signal of which a voltage is increased with a first slope is applied to the word line to when a current flows through the memory cells in response to applying the first signal, and a second time difference from when a second signal of which a voltage is increased with a second slope is applied to the word line to when a current flows through the memory cells in response to applying the second signal, the second slope being different from the first slope, and a determination circuit configured to determine a threshold voltage of the memory cells based on a difference between the first time difference and the second time difference.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: August 24, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Rui Ito, Makoto Morimoto, Yutaka Shimizu, Ryuichi Fujimoto
  • Publication number: 20210090633
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of memory cells connected to a word line, a circuit configured to apply a voltage to the word line, a detection circuit configured to detect a first time difference from when a first signal of which a voltage is increased with a first slope is applied to the word line to when a current flows through the memory cells in response to applying the first signal, and a second time difference from when a second signal of which a voltage is increased with a second slope is applied to the word line to when a current flows through the memory cells in response to applying the second signal, the second slope being different from the first slope, and a determination circuit configured to determine a threshold voltage of the memory cells based on a difference between the first time difference and the second time difference.
    Type: Application
    Filed: February 27, 2020
    Publication date: March 25, 2021
    Applicant: KIOXIA CORPORATION
    Inventors: Rui ITO, Makoto MORIMOTO, Yutaka SHIMIZU, Ryuichi FUJIMOTO
  • Publication number: 20210050048
    Abstract: According to one embodiment, a sense amplifier circuit includes an amplifier having an input terminal connected to a sense node, and a first capacitor configured to be connected in a feedback path of the amplification transistor and to a bit line of a memory cell via the sense node, the first capacitor configured to supply a current to the memory cell and integrate the current when the memory cell is read.
    Type: Application
    Filed: February 24, 2020
    Publication date: February 18, 2021
    Applicant: KIOXIA CORPORATION
    Inventors: Rui ITO, Takeshi HIOKA, Takuyo KODAMA
  • Publication number: 20200090764
    Abstract: A semiconductor memory device includes a plurality of memory cells that include one or more pairs of reference cells that store reference data, and a circuit peripheral thereto. The memory cells are commonly connected to a word line and connected to a plurality of bit lines, respectively. The circuit is configured to apply a read voltage to the word line, cause sense nodes of bit lines connected to the reference memory cells of each pair to be electrically connected to each other, determine whether or not each of the plurality of reference memory cells is ON or OFF based on a voltage at a sense node of each of the plurality of bit lines, and update the read voltage based on the number of reference memory cells determined to be ON and the number thereof determined to be OFF.
    Type: Application
    Filed: March 4, 2019
    Publication date: March 19, 2020
    Inventor: Rui ITO
  • Patent number: 10340865
    Abstract: An amplifier of an embodiment includes: a plurality of input transistors of a plurality of differential pairs; a plurality of first resistance circuits mutually connecting respective sources of the input transistors corresponding to the differential pairs and mutually connecting the respective sources and reference potential points; a plurality of second resistance circuits being connected between the respective sources of the plurality of input transistors and the reference potential points, respectively; and a control circuit configured to generate a control signal controlling whether or not to electrically connect the plurality of first resistance circuits and the plurality of second resistance circuits to the respective sources of the input transistors.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: July 2, 2019
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Atsushi Shirane, Rui Ito, Toshiya Mitomo
  • Patent number: 10333745
    Abstract: A receiving circuit includes first and second input sections through which signals are to be received, first and second signal lines connected to the first and second input sections, respectively, a first circuit connected to the first and second signal lines and including a termination circuit and a self-test circuit, first and second capacitive elements that are provided in the first and second signal lines and configured to allow alternating-current components of the received signals to pass therethrough and interrupt at least direct-current components of the received signals from passing through, a second circuit that is connected to the first and second signal lines and configured to boost a gain of the received signals in a certain frequency band that have passed through the first and second capacitive elements, and first and second output sections through which the received signals boosted by the second circuit are output.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: June 25, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Rui Ito
  • Publication number: 20180358940
    Abstract: An amplifier of an embodiment includes: a plurality of input transistors of a plurality of differential pairs; a plurality of first resistance circuits mutually connecting respective sources of the input transistors corresponding to the differential pairs and mutually connecting the respective sources and reference potential points; a plurality of second resistance circuits being connected between the respective sources of the plurality of input transistors and the reference potential points, respectively; and a control circuit configured to generate a control signal controlling whether or not to electrically connect the plurality of first resistance circuits and the plurality of second resistance circuits to the respective sources of the input transistors.
    Type: Application
    Filed: August 21, 2018
    Publication date: December 13, 2018
    Inventors: Atsushi Shirane, Rui Ito, Toshiya Mitomo
  • Publication number: 20180278220
    Abstract: An amplifier of an embodiment includes: a plurality of input transistors of a plurality of differential pairs; a plurality of first resistance circuits mutually connecting respective sources of the input transistors corresponding to the differential pairs and mutually connecting the respective sources and reference potential points; a plurality of second resistance circuits being connected between the respective sources of the plurality of input transistors and the reference potential points, respectively; and a control circuit configured to generate a control signal controlling whether or not to electrically connect the plurality of first resistance circuits and the plurality of second resistance circuits to the respective sources of the input transistors.
    Type: Application
    Filed: September 11, 2017
    Publication date: September 27, 2018
    Inventors: Atsushi Shirane, Rui Ito, Toshiya Mitomo
  • Patent number: 10084419
    Abstract: An amplifier of an embodiment includes: a plurality of input transistors of a plurality of differential pairs; a plurality of first resistance circuits mutually connecting respective sources of the input transistors corresponding to the differential pairs and mutually connecting the respective sources and reference potential points; a plurality of second resistance circuits being connected between the respective sources of the plurality of input transistors and the reference potential points, respectively; and a control circuit configured to generate a control signal controlling whether or not to electrically connect the plurality of first resistance circuits and the plurality of second resistance circuits to the respective sources of the input transistors.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: September 25, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Shirane, Rui Ito, Toshiya Mitomo
  • Patent number: 9621116
    Abstract: According to one embodiment, there is provided an active load circuit including a first transistor, a second transistor, a first resistor, a second resistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a line. The third transistor is placed between the first transistor and the first reference node. The fourth transistor is placed between the second transistor and the first reference node. The seventh transistor is placed between the fifth transistor and the first reference node. The eighth transistor is placed between the sixth transistor and the first reference node. A line connecting a fifth node between the fifth transistor and the seventh transistor and a sixth node between the sixth transistor and the eighth transistor.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: April 11, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Rui Ito, Naohiro Matsui
  • Publication number: 20160268977
    Abstract: According to one embodiment, there is provided an active load circuit including a first transistor, a second transistor, a first resistor, a second resistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a line. The third transistor is placed between the first transistor and the first reference node. The fourth transistor is placed between the second transistor and the first reference node. The seventh transistor is placed between the fifth transistor and the first reference node. The eighth transistor is placed between the sixth transistor and the first reference node. a line connecting a fifth node between the fifth transistor and the seventh transistor and a sixth node between the sixth transistor and the eighth transistor.
    Type: Application
    Filed: September 3, 2015
    Publication date: September 15, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Rui ITO, Naohiro MATSUI
  • Publication number: 20140062610
    Abstract: According to one embodiment, a switching unit switches between a first state in which the current source is connected to a first capacitance element and a ground electric potential is connected to a second capacitance element and a second state in which a current source is connected to the second capacitance element and the ground electric potential is connected to the first capacitance element. A comparison unit compares a voltage charged in the first capacitance element and a reference voltage with each other in the first state and compares a voltage charged in the second capacitance element and the reference voltage with each other in the second state. A generation unit generates a periodical pulse based on a comparison result acquired by the comparison unit. The switching unit alternately switches between the first state and the second state based on the comparison result acquired by the comparison unit.
    Type: Application
    Filed: March 13, 2013
    Publication date: March 6, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Rui ITO
  • Patent number: 7865163
    Abstract: A time constant automatic adjusting circuit comprises: a filter circuit varying a phase of an clock signal to be input so as to output the clock signal; a phase comparison circuit comparing a phase of an output signal of the filter circuit with the phase of the clock signal, and outputting a predetermined voltage when the phase of the output signal and the phase of the clock signal are the same; at least three comparators comparing the output voltage with a plurality of different voltages; an up-down counter counting a number of output bits of either one of the at least three different voltages in accordance with an output result of the comparators; and a control circuit varying the time constant of the filter circuit in accordance with the number of output bits counted by the up-down counter.
    Type: Grant
    Filed: March 19, 2009
    Date of Patent: January 4, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Osamu Watanabe, Rui Ito, Shigehito Saigusa, Tetsuro Itakura
  • Patent number: 7778358
    Abstract: A receiver includes a memory for storing DC offset amounts generated by an analog circuit; an amplifier; a DC offset amount generator for generating a first offset value and a second offset value to be removed from the received signal amplified at the amplifier; a first DC offset component-removing unit for removing the first DC offset value from the received signal before the amplifier; a second DC offset component-removing unit for removing the second DC offset value from the received signal after the amplifier; and an updating unit for updating the DC offset amount stored in the memory in view of the second DC offset value generated by the DC offset amount generator. A maximum value of the second DC offset value is set larger than a multiplication value of a gain of the amplifier by a minimum resolution value of the first DC offset value.
    Type: Grant
    Filed: September 7, 2007
    Date of Patent: August 17, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidenori Okuni, Rui Ito, Hiroshi Yoshida
  • Patent number: 7764748
    Abstract: A receiver includes a memory for storing DC offset amounts in accordance with a DC offset component remaining in a received signal; a first DC offset component-removing unit configured so as to generate a first DC offset amount from the DC offset amounts stored in the memory and to remove the first DC offset amount from the received signal; an amplifier for amplifying a signal output from the first DC offset component-removing unit; and a second DC offset component-removing unit configured so as to generate a second DC offset amount from the DC offset amounts stored in the memory in view of a gain of the amplifier and remove the second DC offset amount from the signal amplified by the amplifier.
    Type: Grant
    Filed: September 7, 2007
    Date of Patent: July 27, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidenori Okuni, Rui Ito, Hiroshi Yoshida
  • Patent number: 7733186
    Abstract: A bias circuit including: a first current source which generates a first current; a second current source which generates a second current having a temperature-to-output current characteristic that an output current characteristic increases or decreases with a change in temperature to intersect with that of the first current; a first current-voltage conversion circuit which converts the first current to a first voltage; a second current-voltage conversion circuit which has an input terminal and converts a current inputted into the input terminal to a second voltage; a comparison circuit which compares the first voltage and the second voltage and generates a third current according to a result of the comparison; an addition unit which adds the third current to the second current and inputs a resulting current to the input terminal; and a voltage-current conversion circuit which converts the second voltage to a fourth current for bias.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: June 8, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Hosoya, Rui Ito