Patents by Inventor Rui Niu

Rui Niu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240146663
    Abstract: The present disclosure relates to a gateway device and a method therefor, a medium and an application product. The gateway device includes: a processor; and a memory coupled to the processor and stored with instructions that, when executed by the processor, cause the gateway device to perform the following operations: during connection of the gateway device to an external network via a mobile network: receiving, from a first networked device, a data packet to be forwarded to the second networked device via the gateway device; determining that the data packet has a data volume greater than a threshold data volume; and intercepting the data packet.
    Type: Application
    Filed: October 19, 2023
    Publication date: May 2, 2024
    Inventors: Linzhou CAI, Lijie NIU, Rui CHEN, Shenxia TAN, Fen HUANG
  • Publication number: 20240137760
    Abstract: A device and method and computer readable medium for resisting downgrade attacks. User equipment includes a memory having instructions stored thereon and a processor configured to execute the instructions stored on the memory to cause the user equipment to perform the following operations: determining a security authentication type when the user equipment is connected to a network device for the first time; and in response to determining that the security authentication type when the user equipment is connected to the network device for the first time is WPA3, applying the only-WPA3 rule; where the only-WPA3 rule only allows the user equipment to use WPA3 to access the network device, and refuses the user equipment to use other security authentication types with lower security than WPA3 to access the network device.
    Type: Application
    Filed: October 12, 2023
    Publication date: April 25, 2024
    Inventors: Rui CHEN, Lijie NIU, Linzhou CAI, Li WANG
  • Patent number: 11911426
    Abstract: The disclosure provides the use of a plant in the preparation of medicines and health products for preventing and treating ovarian injury. The application found that seabuckthorn fruit pulp and seabuckthorn seed oil have good preventive and therapeutic effects on ovarian injury. Seabuckthorn fruit pulp and seabuckthorn seed oil can prevent mouse ovarian injury and estrus cycle disorders, and can improve ovarian reserve, etc. Meanwhile, they also have good therapeutic effects on the above-mentioned injuries. This application provides a basis for the prevention and treatment of ovarian injury directly by seabuckthorn fruit pulp and seabuckthorn seed oil.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: February 27, 2024
    Assignee: Ningxia Medical University
    Inventors: Rui He, Guangyong Li, Puguang Yu, Yang Niu, Huiming Ma
  • Publication number: 20220189901
    Abstract: A packaged IC includes a fanout layer, a processor having a first surface residing substantially adjacent a first surface of the fanout layer, a Redistribution Layer (RDL) having a first surface coupled to a second surface of the processor, and a memory coupled to a second surface of the RDL, wherein a first portion of the memory is disposed outside of a footprint of the processor and a second portion of the memory is disposed within the footprint of the processor. The packaged IC further includes first conductive posts disposed beneath the first portion of the memory proximate a first side of the processor for providing communication links between the processor and memory, and second conductive posts coupled between the fanout layer and conductive features of the RDL coupled to power inputs of the second portion of the memory, the second conductive posts proximate a second side of the processor.
    Type: Application
    Filed: March 4, 2022
    Publication date: June 16, 2022
    Applicant: Huawei Technologies Co., Ltd.
    Inventors: Shiqun Gu, Rui Niu, Xiaodong Zhang, Yiwei Ren, Tonglong Zhang
  • Publication number: 20210358894
    Abstract: A packaged IC includes a fanout layer, an Application Processor (AP) die having a first surface residing substantially adjacent a first surface of the fanout layer, a Redistribution Layer (RDL) having a first surface coupled to a second surface of the AP die Process, and high bandwidth memory coupled to a second surface of the RDL and configured to communicate wirelessly with the AP die. The packaged IC further includes an encapsulant surrounding a substantial portion of the high bandwidth memory, the RDL, and the AP die, the encapsulant contacting the fanout layer on a first side and having an exposed second side, a plurality of conductive posts extending from the fanout layer to the RDL through a portion of the encapsulant, and a plurality of Through Mold Vias (TMVs) extending between the fanout layer and the exposed second side of the encapsulant.
    Type: Application
    Filed: July 29, 2021
    Publication date: November 18, 2021
    Inventors: Shiqun Gu, Rui Niu, Tianqiang Huang
  • Patent number: 10212818
    Abstract: A structure for a core layer of a substrate and a method for fabricating a core layer of a substrate are disclosed. The core layer comprises a molding compound encapsulating a die or a plurality of dies, a dielectric layer on the surfaces of the molding compound, and a conductive layer on top of the dielectric layer. A through hole is formed through the dielectric layer and the molding compound, which may be filled with a metal plate. A laser via is formed similarly. Build-up layers may be assembled next to the core layer to form the substrate, which can be used to package dies.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: February 19, 2019
    Assignee: FUTUREWEI TECHNOLOGIES, INC.
    Inventors: Fei Yu, Anwar A. Mohammed, Rui Niu
  • Publication number: 20180288880
    Abstract: A structure for a core layer of a substrate and a method for fabricating a core layer of a substrate are disclosed. The core layer comprises a molding compound encapsulating a die or a plurality of dies, a dielectric layer on the surfaces of the molding compound, and a conductive layer on top of the dielectric layer. A through hole is formed through the dielectric layer and the molding compound, which may be filled with a metal plate. A laser via is formed similarly. Build-up layers may be assembled next to the core layer to form the substrate, which can be used to package dies.
    Type: Application
    Filed: June 6, 2018
    Publication date: October 4, 2018
    Inventors: Fei Yu, Anwar A. Mohammed, Rui Niu
  • Patent number: 9458106
    Abstract: The invention provides novel compounds having the general formula: wherein R1, R2, A and W are as described herein, compositions including the compounds and methods of using the compounds.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: October 4, 2016
    Assignee: Hoffmann-La Roche Inc.
    Inventors: Hui Hu, Min Jiang, Taiguang Jin, Rui Niu, Jianhua Wang, Min Wang, Song Yang, Taichang Yuan, Chengang Zhou, Zheng Zhou
  • Publication number: 20150158815
    Abstract: The invention provides novel compounds having the general formula: wherein R1, R2, A and W are as described herein, compositions including the compounds and methods of using the compounds.
    Type: Application
    Filed: February 20, 2015
    Publication date: June 11, 2015
    Applicant: HOFFMANN-LA ROCHE INC.
    Inventors: Hui Hu, Min Jiang, Taiguang Jin, Rui Niu, Jianhua Wang, Min Wang, Song Yang, Taichang Yuan, Chengang Zhou, Zheng Zhou
  • Patent number: 8952533
    Abstract: Polyimide-based redistribution layers (RDLs) can be employed to reduce thermo-mechanical stress that is exerted on conductive interconnections bonded to interposers in 2.5 D semiconductor packaging configurations. The polyimide-based RDL is located on an upper or lower face of an interposer. Additionally, height differentials between laterally adjacent semiconductor dies in 2.5 D semiconductor packages can be reduced or eliminated by using different diameter micro-bumps, different height copper pillars, or a multi-tiered interposer to lower taller semiconductor dies in relation to shorter semiconductor dies.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: February 10, 2015
    Assignee: Futurewei Technologies, Inc.
    Inventors: Anwar A. Mohammed, Weifeng Liu, Rui Niu
  • Publication number: 20140070406
    Abstract: Polyimide-based redistribution layers (RDLs) can be employed to reduce thermo-mechanical stress that is exerted on conductive interconnections bonded to interposers in 2.5 D semiconductor packaging configurations. The polyimide-based RDL is located on an upper or lower face of an interposer. Additionally, height differentials between laterally adjacent semiconductor dies in 2.5 D semiconductor packages can be reduced or eliminated by using different diameter micro-bumps, different height copper pillars, or a multi-tiered interposer to lower taller semiconductor dies in relation to shorter semiconductor dies.
    Type: Application
    Filed: May 17, 2013
    Publication date: March 13, 2014
    Inventors: Anwar A. Mohammed, Weifeng Liu, Rui Niu
  • Patent number: 8519543
    Abstract: A multi-die integrated circuit assembly includes an interposer substrate larger than the typical reticle size used in fabricating the “active area” in which the through-silicon vias (TSVs) and interconnect conductors are formed in the interposer. At the same time, each of the dies has its external power/ground and I/O signal line connections concentrated into a smaller area of the die. The dies are disposed or mounted on the interposer such that these smaller areas (with the power/ground/IO connections) overlap with the active area of the interposer. In this configuration, a plurality of dies having a combined area substantially greater than the active area of the interposer can be mounted on the interposer (and take advantage of the active area for interconnections).
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: August 27, 2013
    Assignee: Futurewei Technologies, Inc.
    Inventors: Haoyu Song, Cao Wei, Rui Niu, Anwar A. Mohammed
  • Publication number: 20130186676
    Abstract: A structure for a core layer of a substrate and a method for fabricating a core layer of a substrate are disclosed. The core layer comprises a molding compound encapsulating a die or a plurality of dies, a dielectric layer on the surfaces of the molding compound, and a conductive layer on top of the dielectric layer. A through hole is formed through the dielectric layer and the molding compound, which may be filled with a metal plate. A laser via is formed similarly. Build-up layers may be assembled next to the core layer to form the substrate, which can be used to package dies.
    Type: Application
    Filed: January 20, 2012
    Publication date: July 25, 2013
    Applicant: FutureWei Technologies, Inc.
    Inventors: Fei Yu, Anwar A. Mohammed, Rui Niu