Abstract: The present application provides a clock switching method, a clock switching apparatus, an electronic device, and a readable storage medium, the clock switching method includes: in a case where a first reference clock is determined to be in a locked state, determining an average control word according to a preset duration and an obtained real frequency tuning word; in a case where the first reference clock is determined to be in an invalid state, determining a compensation phase difference by using the average control word as a frequency control word of a digital phase locked loop; performing a phase compensation on a second reference clock according to the compensation phase difference to obtain an updated second reference clock; and switching the first reference clock to the updated second reference clock.

Abstract: The present disclosure provides a linearity calibration method for digital time converter, including: acquiring a phase prediction parameter and a locked phase error, and calculating a control word of a digital time converter according to the phase prediction parameter, the locked phase error, a pre-configured nonlinear predistortion function, and a pre-configured calibration order n, with the control word being configured to enable the digital time converter to adjust a delay of a reference clock, so as to keep the reference clock and a feedback clock which are input to a time digital converter in a tracked state. The present disclosure further provides a linearity calibration apparatus for digital time converter and a digital phase lock loop.

Abstract: The present application provides a clock switching method, a clock switching apparatus, an electronic device, and a readable storage medium, the clock switching method includes: in a case where a first reference clock is determined to be in a locked state, determining an average control word according to a preset duration and an obtained real frequency tuning word; in a case where the first reference clock is determined to be in an invalid state, determining a compensation phase difference by using the average control word as a frequency control word of a digital phase locked loop; performing a phase compensation on a second reference clock according to the compensation phase difference to obtain an updated second reference clock; and switching the first reference clock to the updated second reference clock.

Abstract: A phase detection method and apparatus, and a storage medium and an electronic apparatus are provided. A sampling operation is performed on a clock signal to be detected to obtain binary sequences. Phase intervals of the clock signal to be detected in initial sampling periods are determined, according to the binary sequences, as first phase intervals. Based on a reference phase interval in the first phase intervals, a standardization operation is performed on other phase intervals in the first phase intervals to obtain second phase intervals, wherein the reference phase interval is a phase interval determined within a first sampling period after the sampling operation is triggered, and the other phase intervals are phase intervals determined within sampling periods following the first sampling period. The second phase intervals are converged, and phase information of the clock signal to be detected is obtained according to the converged second phase intervals.

Abstract: A phase detection method and apparatus, and a storage medium and an electronic apparatus are provided. A sampling operation is performed on a clock signal to be detected to obtain binary sequences. Phase intervals of the clock signal to be detected in initial sampling periods are determined, according to the binary sequences, as first phase intervals. Based on a reference phase interval in the first phase intervals, a standardization operation is performed on other phase intervals in the first phase intervals to obtain second phase intervals, wherein the reference phase interval is a phase interval determined within a first sampling period after the sampling operation is triggered, and the other phase intervals are phase intervals determined within sampling periods following the first sampling period. The second phase intervals are converged, and phase information of the clock signal to be detected is obtained according to the converged second phase intervals.

Abstract: A display substrate includes an annular package region and a display region inside package region. The package region includes an annular adhering region and a groove region positioned inside and/or outside the adhering region. A groove structure in which water-absorbing material and/or oxygen-absorbing material is provided is formed in the groove region. The display substrate can solve the problems of poor moisture isolation effect and influence of oxygen in the conventional display device. A display device including the display substrate is further provided.

Abstract: A display substrate comprises an annular package region and a display region inside package region. The package region includes an annular adhering region and a groove region positioned inside and/or outside the adhering region. A groove structure in which water-absorbing material and/or oxygen-absorbing material is provided is formed in the groove region. The display substrate can solve the problems of poor moisture isolation effect and influence of oxygen in the conventional display device. A display device including the display substrate is further provided.