Patents by Inventor Rui Sakai

Rui Sakai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8201047
    Abstract: A decoding apparatus includes a row processing unit 5 and a column processing unit 6 for performing a calculation and an update of probability information with row processing and column processing according to a Min-Sum algorithm on a received signal which is low-density parity-check coded in batches of 1 bit or a predetermined number of bits, a decoded result judgment unit 8 for determining a decoded result from a hard decision of a posterior value, for performing a parity check on the decoded result, and for judging whether or not the decoded result is correct, and a control unit for controlling iteration of decoding processing by the row processing unit 5 and column processing unit 6 on the basis of the judgment result of the decoded result judgment unit 8.
    Type: Grant
    Filed: December 1, 2005
    Date of Patent: June 12, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Rui Sakai, Wataru Matsumoto, Yoshikuni Miyata, Hideo Yoshida, Takahiko Nakamura
  • Patent number: 8196014
    Abstract: When arranging J cyclic permutation matrices I(pj,l) with p rows and q columns (0?j?J?1, 0?l?L?1) in a row direction and also arranging L cyclic permutation matrices I(pj,l) in a column direction so as to generate a regular quasi-cyclic matrix having uniform row and column weights, a quasi-cyclic matrix generating unit 31 configures the regular quasi-cyclic matrix by combining cyclic permutation matrices I(pj,l) in each of which matrix elements whose row number is r (0?r?p?1) and whose column number is (r+pj,l) mod p are “1”s, and other matrix elements are “0”s in such a way that a plurality of cyclic permutation matrices I(pj,l) arranged at, e.g., the 1st row differ from one another.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: June 5, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Wataru Matsumoto, Rui Sakai, Hideo Yoshida
  • Patent number: 8171371
    Abstract: A regular qc matrix is generated in which cyclic permutation matrices with specific regularity are arranged in row and column directions. A mask matrix supporting multiple encoding rates is generated for making the regular qc matrix into irregular. A specific cyclic permutation matrix in the regular qc matrix is converted into a zero-matrix using a mask matrix corresponding to a specific encoding rate to generate an irregular masking qc matrix. An irregular parity check matrix with a LDGM structure is generated, in which the masking qc matrix and a matrix in which the cyclic permutation matrices are arranged in a staircase manner are arranged in a predetermined location.
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: May 1, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Wataru Matsumoto, Rui Sakai, Hideo Yoshida
  • Patent number: 8132080
    Abstract: A communication apparatus includes a storage unit, a row processing unit, and a column processing unit. The row processing unit repeatedly performs row processing to calculate a column-processing LLR for each column and each row in a check matrix. The column processing unit calculates a row-processing LLR for each column and each row of the check matrix, and repeatedly performs column processing to store in the storage unit the minimum value k of absolute values of the row-processing LLR. The row processing unit and the column processing unit alternately performs their processing. The row processing unit performs calculation using an approximate minimum value while the column processing unit cyclically updates the minimum k value of each row.
    Type: Grant
    Filed: July 12, 2006
    Date of Patent: March 6, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Wataru Matsumoto, Rui Sakai, Hideo Yoshida, Yoshikuni Miyata
  • Patent number: 8122324
    Abstract: An error correction coding apparatus is disposed to generate a low-density parity-check code 16 from an input information sequence 15 by using a low-density parity-check matrix which satisfies a predetermined weight distribution, and includes a low-density parity-check matrix output means 13 for forming the above-mentioned low-density parity-check matrix by continuously arranging a number of rows in each of which the same number of cyclic-permutation matrices as the row weight are arranged, the number of rows satisfying the above-mentioned predetermined weight distribution, and then gradually increasing or decreasing the row weight, and for outputting the above-mentioned low-density parity-check matrix.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: February 21, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Wataru Matsumoto, Rui Sakai, Hideo Yoshida
  • Patent number: 8103935
    Abstract: A regular quasi-cyclic matrix is prepared, a conditional expression for assuring a predetermined minimum loop in a parity check matrix is derived, and a mask matrix for converting a specific cyclic permutation matrix into a zero-matrix based on the conditional expression and a predetermined weight distribution is generated. The specific cyclic permutation matrix is converted into the zero-matrix to generate an irregular masking quasi-cyclic matrix. An irregular parity check matrix in which the masking quasi-cyclic matrix and a matrix in which the cyclic permutation matrices are arranged in a staircase manner are arranged in a predetermined location.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: January 24, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Wataru Matsumoto, Rui Sakai, Hideo Yoshida, Takahiko Nakamura, Yoshikuni Miyata
  • Publication number: 20100229066
    Abstract: An irregular parity check matrix is generated which has an LDGM structure in which a masking quasi-cyclic matrix and a matrix in which cyclic permutation matrices are arranged in a staircase manner are arranged in a predetermined location. A mask matrix capable of supporting a single encoding rate for making the regular quasi-cyclic matrix into an irregular quasi-cyclic matrix is generated. The irregular parity check matrix is masked using a generated mask matrix, and a parity check matrix is generated combining a masked irregular parity check matrix with a lower triangular matrix formed in a staircase manner to satisfy a single encoding rate.
    Type: Application
    Filed: January 5, 2007
    Publication date: September 9, 2010
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Wataru Matsumoto, Rui Sakai, Hideo Yoshida
  • Publication number: 20100211846
    Abstract: When arranging J cyclic permutation matrices I(pj,l) with p rows and q columns (0?j?J?1, 0?l?L?1) in a row direction and also arranging L cyclic permutation matrices I(pj,l) in a column direction so as to generate a regular quasi-cyclic matrix having uniform row and column weights, a quasi-cyclic matrix generating unit 31 configures the regular quasi-cyclic matrix by combining cyclic permutation matrices I(pj,l) in each of which matrix elements whose row number is r (0?r?p?1) and whose column number is (r+pj,l) mod p are “1”s, and other matrix elements are “0”s in such a way that a plurality of cyclic permutation matrices I(pj,l) arranged at, e.g., the 1st row differ from one another.
    Type: Application
    Filed: June 26, 2008
    Publication date: August 19, 2010
    Applicant: Mitsubishi Electric Corporation
    Inventors: Wataru Matsumoto, Rui Sakai, Hideo Yoshida
  • Publication number: 20100058140
    Abstract: A regular quasi-cyclic matrix is generated in which specific regularity is given to cyclic permutation matrices. A mask matrix capable of supporting a plurality of encoding rates is generated. A specific cyclic permutation matrix in the regular quasi-cyclic matrix is converted into a zero-matrix using a mask matrix corresponding to a specific encoding rate to generate an irregular masking quasi-cyclic matrix. An irregular parity check matrix with an LDGM structure is generated in which the masking quasi-cyclic matrix and a matrix in which the cyclic permutation matrices are arranged in a staircase manner are arranged in a predetermined location.
    Type: Application
    Filed: August 2, 2007
    Publication date: March 4, 2010
    Applicant: Mitsubishi Electric Corporation
    Inventors: Wataru Matsumoto, Rui Sakai, Hideo Yoshida
  • Publication number: 20090265600
    Abstract: A regular quasi-cyclic matrix is prepared, a conditional expression for assuring a predetermined minimum loop in a parity check matrix is derived, and a mask matrix for converting a specific cyclic permutation matrix into a zero-matrix based on the conditional expression and a predetermined weight distribution is generated. The specific cyclic permutation matrix is converted into the zero-matrix to generate an irregular masking quasi-cyclic matrix. An irregular parity check matrix in which the masking quasi-cyclic matrix and a matrix in which the cyclic permutation matrices are arranged in a staircase manner are arranged in a predetermined location.
    Type: Application
    Filed: July 31, 2006
    Publication date: October 22, 2009
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Wataru Matsumoto, Rui Sakai, Hideo Yoshida, Takahiko Nakamura, Yoshikuni Miyata
  • Publication number: 20090164864
    Abstract: A regular qc matrix is generated in which cyclic permutation matrices with specific regularity are arranged in row and column directions. A mask matrix supporting multiple encoding rates is generated for making the regular qc matrix into irregular. A specific cyclic permutation matrix in the regular qc matrix is converted into a zero-matrix using a mask matrix corresponding to a specific encoding rate to generate an irregular masking qc matrix. An irregular parity check matrix with a LDGM structure is generated, in which the masking qc matrix and a matrix in which the cyclic permutation matrices are arranged in a staircase manner are arranged in a predetermined location.
    Type: Application
    Filed: December 13, 2006
    Publication date: June 25, 2009
    Applicant: Mitsubishi Electric Corporation
    Inventors: Wataru Matsumoto, Rui Sakai, Hideo Yoshida
  • Publication number: 20090132887
    Abstract: A communication apparatus includes a storage unit, a row processing unit, and a column processing unit. The row processing unit repeatedly performs row processing to calculate a column-processing LLR for each column and each row in a check matrix. The column processing unit calculates a row-processing LLR for each column and each row of the check matrix, and repeatedly performs column processing to store in the storage unit the minimum value k of absolute values of the row-processing LLR. The row processing unit and the column processing unit alternately performs their processing. The row processing unit performs calculation using an approximate minimum value while the column processing unit cyclically updates the minimum k value of each row.
    Type: Application
    Filed: July 12, 2006
    Publication date: May 21, 2009
    Applicant: Mitsubishi Electric Corporation
    Inventors: Wataru Matsumoto, Rui Sakai, Hideo Yoshida, Yoshikuni Miyata
  • Publication number: 20090063930
    Abstract: A regular quasi-cyclic matrix is generated with cyclic permutation matrices and specific regularity given to the cyclic permutation matrices. A mask matrix for making the regular quasi-cyclic matrix into an irregular quasi-cyclic matrix is generated. An irregular masked quasi-cyclic matrix is generated by converting a specific cyclic permutation matrix in the regular quasi-cyclic matrix into a zero-matrix using a mask matrix supporting a specific encoding rate. An irregular parity check matrix with an LDGM structure is generated with a masked quasi-cyclic matrix and a matrix in which the cyclic permutation matrices are arranged in a staircase manner.
    Type: Application
    Filed: January 31, 2007
    Publication date: March 5, 2009
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Wataru Matsumoto, Rui Sakai, Hideo Yoshida
  • Publication number: 20090031186
    Abstract: An error correction coding apparatus is disposed to generate a low-density parity-check code 16 from an input information sequence 15 by using a low-density parity-check matrix which satisfies a predetermined weight distribution, and includes a low-density parity-check matrix output means 13 for forming the above-mentioned low-density parity-check matrix by continuously arranging a number of rows in each of which the same number of cyclic-permutation matrices as the row weight are arranged, the number of rows satisfying the above-mentioned predetermined weight distribution, and then gradually increasing or decreasing the row weight, and for outputting the above-mentioned low-density parity-check matrix.
    Type: Application
    Filed: March 30, 2006
    Publication date: January 29, 2009
    Inventors: Wataru Matsumoto, Rui Sakai, Hideo Yoshida
  • Publication number: 20080246639
    Abstract: A decoding apparatus includes a row processing unit 5 and a column processing unit 6 for performing a calculation and an update of probability information with row processing and column processing according to a Min-Sum algorithm on a received signal which is low-density parity-check coded in batches of 1 bit or a predetermined number of bits, a decoded result judgment unit 8 for determining a decoded result from a hard decision of a posterior value, for performing a parity check on the decoded result, and for judging whether or not the decoded result is correct, and a control unit for controlling iteration of decoding processing by the row processing unit 5 and column processing unit 6 on the basis of the judgment result of the decoded result judgment unit 8.
    Type: Application
    Filed: December 1, 2005
    Publication date: October 9, 2008
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Rui Sakai, Wataru Matsumoto, Yoshikuni Miyata, Hideo Yoshida, Takahiko Nakamura