Patents by Inventor Rui Tze TOH

Rui Tze TOH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Grounding of silicon-on-insulator structure
    Patent number: 9087906
    Abstract: Devices and methods for forming a device are presented. The method includes providing a substrate having at least a first region and a second region prepared with isolation regions. The first region is referred to as a chip guarding area and the second region defines a chip region of which at least one transistor is to be formed. The substrate includes a top surface layer, a support substrate and an insulator layer in between them. A transistor is formed in the second region and a substrate contact structure is formed in the first region. The substrate contact structure passes through at least the top surface layer, insulator layer and isolation region and contacts a doped region in the support substrate. The substrate contact structure is connected to at least one conductive line with a desired potential to prevent charging of the support substrate at system level.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: July 21, 2015
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Purakh Raj Verma, Shaoqiang Zhang, Bo Yu, Guan Huei See, Rui Tze Toh, Tao Jiang
  • GROUNDING OF SILICON-ON-INSULATOR STRUCTURE
    Publication number: 20150097240
    Abstract: Devices and methods for forming a device are presented. The method includes providing a substrate having at least a first region and a second region prepared with isolation regions. The first region is referred to as a chip guarding area and the second region defines a chip region of which at least one transistor is to be formed. The substrate includes a top surface layer, a support substrate and an insulator layer in between them. A transistor is formed in the second region and a substrate contact structure is formed in the first region. The substrate contact structure passes through at least the top surface layer, insulator layer and isolation region and contacts a doped region in the support substrate. The substrate contact structure is connected to at least one conductive line with a desired potential to prevent charging of the support substrate at system level.
    Type: Application
    Filed: October 2, 2014
    Publication date: April 9, 2015
    Inventors: Purakh Raj VERMA, Shaoqiang ZHANG, Bo YU, Guan Huei SEE, Rui Tze TOH, Tao JIANG