Abstract: The present application provides a pixel structure and a display panel. The pixel structure includes pixel units, data lines, and scan lines. The pixel unit includes a main pixel region and a sub-pixel region. Each data line includes a first data line section, a second data line section, and a third data line section. Each first data line section is arranged between the two main pixel regions of two adjacent pixel units. The second data line section and the third data line section are arranged in the two sub-pixel regions of adjacent two pixel units, respectively.

Abstract: A pixel structure and a display panel are provided. The pixel structure includes a first pixel electrode, a first longitudinal signal line, and a second longitudinal signal line. The first pixel electrode includes a first main pixel area and a first sub-pixel area. The first longitudinal signal line includes a first main line and a first secondary-line. The second longitudinal signal line includes a second main line and a second secondary-line. The first main line and the second main line are arranged in the first main pixel area, and the first secondary-line and the second secondary-line are arranged in the first sub-pixel area.

Abstract: The present application discloses an array substrate and a display panel. The array substrate includes a plurality of pixel units arranged in an array, each of the pixel units includes a thin film transistor. The thin film transistor includes a gate electrode and a drain electrode. A first overlap region and a non-overlap region is defined between the gate electrode and the drain electrode. The first overlap region is adjacent to the non-overlap region. A width of a cross section of the drain electrode in the first overlap region is less than a width of a cross section of the drain electrode in the non-overlap region. The array substrate can reduce a parasitic capacitor between the gate electrode and drain electrode.