Patents by Inventor Ruihong NIE

Ruihong NIE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Metal oxide semiconductor integrated circuit basic unit
    Patent number: 11335785
    Abstract: A MOS integrated circuit basic unit includes: a drain semiconductor region; a lightly doped drain region; a channel semiconductor region; a source semiconductor region; a source electrode; a gate electrode; a gate dielectric layer; and a drain electrode. The drain semiconductor region is the bottom of the basic unit. The gate electrode has a ring structure, which surrounds the channel semiconductor region, the source semiconductor region and the lightly doped drain region. The upper surface of the gate electrode is aligned to the upper surface of the source semiconductor region; and a bottom surface of the gate electrode is lower than an interface of the lightly doped drain region and the drain semiconductor region. The gate dielectric layer is disposed between the gate electrode and the adjacent functional layer. The drain semiconductor region is connected to the drain electrode of the basic unit.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: May 17, 2022
    Assignee: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA
    Inventors: Ping Li, Yongbo Liao, Chenxi Peng, Yaosen Li, Ruihong Nie, Ke Feng, Xianghe Zeng, Ruifeng Tang, Jiarui Zou, Zhaoxi Hu, Fan Lin
  • METAL OXIDE SEMICONDUCTOR INTEGRATED CIRCUIT BASIC UNIT
    Publication number: 20210226022
    Abstract: A MOS integrated circuit basic unit includes: a drain semiconductor region; a lightly doped drain region; a channel semiconductor region; a source semiconductor region; a source electrode; a gate electrode; a gate dielectric layer; and a drain electrode. The drain semiconductor region is the bottom of the basic unit. The gate electrode has a ring structure, which surrounds the channel semiconductor region, the source semiconductor region and the lightly doped drain region. The upper surface of the gate electrode is aligned to the upper surface of the source semiconductor region; and a bottom surface of the gate electrode is lower than an interface of the lightly doped drain region and the drain semiconductor region. The gate dielectric layer is disposed between the gate electrode and the adjacent functional layer. The drain semiconductor region is connected to the drain electrode of the basic unit.
    Type: Application
    Filed: December 18, 2020
    Publication date: July 22, 2021
    Inventors: Ping LI, Yongbo LIAO, Chenxi PENG, Yaosen LI, Ruihong NIE, Ke FENG, Xianghe ZENG, Ruifeng TANG, Jiarui ZOU, Zhaoxi HU, Fan LIN