Patents by Inventor Ruihua Peng
Ruihua Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11971834Abstract: A computing device is provided, including a plurality of memory devices, a plurality of direct memory access (DMA) controllers, and an on-chip interconnect. The on-chip interconnect may be configured to implement control logic to convey a read request from a primary DMA controller of the plurality of DMA controllers to a source memory device of the plurality of memory devices. The on-chip interconnect may be further configured to implement the control logic to convey a read response from the source memory device to the primary DMA controller and one or more secondary DMA controllers of the plurality of DMA controllers.Type: GrantFiled: March 13, 2023Date of Patent: April 30, 2024Assignee: Microsoft Technology Licensing, LLCInventors: Ruihua Peng, Monica Man Kay Tang, Xiaoling Xu
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Publication number: 20240045719Abstract: A computing device, including a processor configured to perform data transfer scheduling for a hardware accelerator including a plurality of processing areas. Performing data transfer scheduling may include receiving a plurality of data transfer instructions that encode requests to transfer data to respective processing areas. Performing data transfer scheduling may further include identifying a plurality of transfer path conflicts between the data transfer instructions. Performing data transfer scheduling may further include sorting the data transfer instructions into a plurality of transfer instruction subsets. Within each transfer instruction subset, none of the data transfer instructions have transfer path conflicts. For each transfer instruction subset, performing data transfer scheduling may further include conveying the data transfer instructions included in that transfer instruction subset to the hardware accelerator.Type: ApplicationFiled: October 19, 2023Publication date: February 8, 2024Applicant: Microsoft Technology Licensing, LLCInventors: Monica Man Kay TANG, Ruihua PENG, Zhuo RUAN
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Patent number: 11816502Abstract: A computing device, including a processor configured to perform data transfer scheduling for a hardware accelerator including a plurality of processing areas. Performing data transfer scheduling may include receiving a plurality of data transfer instructions that encode requests to transfer data to respective processing areas. Performing data transfer scheduling may further include identifying a plurality of transfer path conflicts between the data transfer instructions. Performing data transfer scheduling may further include sorting the data transfer instructions into a plurality of transfer instruction subsets. Within each transfer instruction subset, none of the data transfer instructions have transfer path conflicts. For each transfer instruction subset, performing data transfer scheduling may further include conveying the data transfer instructions included in that transfer instruction subset to the hardware accelerator.Type: GrantFiled: February 23, 2023Date of Patent: November 14, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Monica Man Kay Tang, Ruihua Peng, Zhuo Ruan
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Publication number: 20230214342Abstract: A computing device is provided, including a plurality of memory devices, a plurality of direct memory access (DMA) controllers, and an on-chip interconnect. The on-chip interconnect may be configured to implement control logic to convey a read request from a primary DMA controller of the plurality of DMA controllers to a source memory device of the plurality of memory devices. The on-chip interconnect may be further configured to implement the control logic to convey a read response from the source memory device to the primary DMA controller and one or more secondary DMA controllers of the plurality of DMA controllers.Type: ApplicationFiled: March 13, 2023Publication date: July 6, 2023Applicant: Microsoft Technology Licensing, LLCInventors: Ruihua PENG, Monica Man Kay TANG, Xiaoling XU
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Publication number: 20230205581Abstract: A computing device, including a processor configured to perform data transfer scheduling for a hardware accelerator including a plurality of processing areas. Performing data transfer scheduling may include receiving a plurality of data transfer instructions that encode requests to transfer data to respective processing areas. Performing data transfer scheduling may further include identifying a plurality of transfer path conflicts between the data transfer instructions. Performing data transfer scheduling may further include sorting the data transfer instructions into a plurality of transfer instruction subsets. Within each transfer instruction subset, none of the data transfer instructions have transfer path conflicts. For each transfer instruction subset, performing data transfer scheduling may further include conveying the data transfer instructions included in that transfer instruction subset to the hardware accelerator.Type: ApplicationFiled: February 23, 2023Publication date: June 29, 2023Applicant: Microsoft Technology Licensing, LLCInventors: Monica Man Kay TANG, Ruihua PENG, Zhuo RUAN
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Patent number: 11675659Abstract: In one form, a memory controller includes a command queue, an arbiter, and a replay queue. The command queue receives and stores memory access requests. The arbiter is coupled to the command queue for providing a sequence of memory commands to a memory channel. The replay queue stores the sequence of memory commands to the memory channel, and continues to store memory access commands that have not yet received responses from the memory channel. When a response indicates a completion of a corresponding memory command without any error, the replay queue removes the corresponding memory command without taking further action. When a response indicates a completion of the corresponding memory command with an error, the replay queue replays at least the corresponding memory command. In another form, a data processing system includes the memory controller, a memory accessing agent, and a memory system to which the memory controller is coupled.Type: GrantFiled: December 9, 2016Date of Patent: June 13, 2023Assignee: Advanced Micro Devices, Inc.Inventors: James R. Magro, Ruihua Peng, Anthony Asaro, Kedarnath Balakrishnan, Scott P. Murphy, YuBin Yao
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Patent number: 11604748Abstract: A computing device is provided, including a plurality of memory devices, a plurality of direct memory access (DMA) controllers, and an on-chip interconnect. The on-chip interconnect may be configured to implement control logic to convey a read request from a primary DMA controller of the plurality of DMA controllers to a source memory device of the plurality of memory devices. The on-chip interconnect may be further configured to implement the control logic to convey a read response from the source memory device to the primary DMA controller and one or more secondary DMA controllers of the plurality of DMA controllers.Type: GrantFiled: October 30, 2020Date of Patent: March 14, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Ruihua Peng, Monica Man Kay Tang, Xiaoling Xu
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Patent number: 11593164Abstract: A computing device, including a processor configured to perform data transfer scheduling for a hardware accelerator including a plurality of processing areas. Performing data transfer scheduling may include receiving a plurality of data transfer instructions that encode requests to transfer data to respective processing areas. Performing data transfer scheduling may further include identifying a plurality of transfer path conflicts between the data transfer instructions. Performing data transfer scheduling may further include sorting the data transfer instructions into a plurality of transfer instruction subsets. Within each transfer instruction subset, none of the data transfer instructions have transfer path conflicts. For each transfer instruction subset, performing data transfer scheduling may further include conveying the data transfer instructions included in that transfer instruction subset to the hardware accelerator.Type: GrantFiled: March 3, 2021Date of Patent: February 28, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Monica Man Kay Tang, Ruihua Peng, Zhuo Ruan
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Publication number: 20230004400Abstract: A system for providing system level sleep state power savings includes a plurality of memory channels and corresponding plurality of memories coupled to respective memory channels. The system includes one or more processors operative to receive information indicating that a system level sleep state is to be entered and in response to receiving the system level sleep indication, moves data stored in at least a first of the plurality of memories to at least a second of the plurality of memories. In some implementations, in response to moving the data to the second memory, the processor causes power management logic to shut off power to: at least the first memory, to a corresponding first physical layer device operatively coupled to the first memory and to a first memory controller operatively coupled to the first memory and place the second memory in a self-refresh mode of operation.Type: ApplicationFiled: September 13, 2022Publication date: January 5, 2023Inventors: JYOTI RAHEJA, HIDEKI KANAYAMA, GUHAN KRISHNAN, RUIHUA PENG
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Publication number: 20220393975Abstract: The present disclosure relates to systems, methods, and computer-readable media for data from a first multi-dimensional memory block to a second multi-dimensional memory block. For example, systems described herein facilitate transferring data between memory blocks having different shapes from one another. The systems described herein facilitate transferring data between different shaped memory blocks by identifying shape properties and other characteristics of the data and generating a plurality of network packets having control data based on the identified shape properties and other characteristics. This data included within the network packets enables memory controllers to determine memory addresses on a destination memory block to write data from the network packets. Features described herein facilitate efficient transfer of data without generating a linearized copy that relies on constant availability of significant memory resources.Type: ApplicationFiled: June 7, 2021Publication date: December 8, 2022Inventors: Deepak GOEL, Ruihua PENG, Xiaoling XU
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Patent number: 11520722Abstract: Embodiments of the present disclosure include techniques for transferring non-power of two (2) bytes of data between modules of an integrated circuit over an on-chip communication fabric. In one embodiment, the present disclosure includes an on-chip communication fabric, a first module comprising an interface coupled to the fabric having a first data width, and a second module comprising an interface coupled to the fabric having a second data width smaller than the first data width. The non-power of two (2) bytes of data are sent between the first and second modules through the fabric, and the fabric maps the non-power of two (2) bytes of data between the first and second data widths.Type: GrantFiled: April 12, 2021Date of Patent: December 6, 2022Assignee: Microsoft Technology Licensing, LLCInventors: Monica Man Kay Tang, Ruihua Peng, Matthew Willis Daniel
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Publication number: 20220327078Abstract: Embodiments of the present disclosure include techniques for transferring non-power of two (2) bytes of data between modules of an integrated circuit over an on-chip communication fabric. In one embodiment, the present disclosure includes an on-chip communication fabric, a first module comprising an interface coupled to the fabric having a first data width, and a second module comprising an interface coupled to the fabric having a second data width smaller than the first data width. The non-power of two (2) bytes of data are sent between the first and second modules through the fabric, and the fabric maps the non-power of two (2) bytes of data between the first and second data widths.Type: ApplicationFiled: April 12, 2021Publication date: October 13, 2022Inventors: Monica Man Kay TANG, Ruihua PENG, Matthew Willis Daniel
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Patent number: 11449346Abstract: A system for providing system level sleep state power savings includes a plurality of memory channels and corresponding plurality of memories coupled to respective memory channels. The system includes one or more processors operative to receive information indicating that a system level sleep state is to be entered and in response to receiving the system level sleep indication, moves data stored in at least a first of the plurality of memories to at least a second of the plurality of memories. In some implementations, in response to moving the data to the second memory, the processor causes power management logic to shut off power to: at least the first memory, to a corresponding first physical layer device operatively coupled to the first memory and to a first memory controller operatively coupled to the first memory and place the second memory in a self-refresh mode of operation.Type: GrantFiled: December 18, 2019Date of Patent: September 20, 2022Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Jyoti Raheja, Hideki Kanayama, Guhan Krishnan, Ruihua Peng
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Publication number: 20220283850Abstract: A computing device, including a processor configured to perform data transfer scheduling for a hardware accelerator including a plurality of processing areas. Performing data transfer scheduling may include receiving a plurality of data transfer instructions that encode requests to transfer data to respective processing areas. Performing data transfer scheduling may further include identifying a plurality of transfer path conflicts between the data transfer instructions. Performing data transfer scheduling may further include sorting the data transfer instructions into a plurality of transfer instruction subsets. Within each transfer instruction subset, none of the data transfer instructions have transfer path conflicts. For each transfer instruction subset, performing data transfer scheduling may further include conveying the data transfer instructions included in that transfer instruction subset to the hardware accelerator.Type: ApplicationFiled: March 3, 2021Publication date: September 8, 2022Applicant: Microsoft Technology Licensing, LLCInventors: Monica Man Kay TANG, Ruihua PENG, Zhuo RUAN
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Publication number: 20220138130Abstract: A computing device is provided, including a plurality of memory devices, a plurality of direct memory access (DMA) controllers, and an on-chip interconnect. The on-chip interconnect may be configured to implement control logic to convey a read request from a primary DMA controller of the plurality of DMA controllers to a source memory device of the plurality of memory devices. The on-chip interconnect may be further configured to implement the control logic to convey a read response from the source memory device to the primary DMA controller and one or more secondary DMA controllers of the plurality of DMA controllers.Type: ApplicationFiled: October 30, 2020Publication date: May 5, 2022Applicant: Microsoft Technology Licensing, LLCInventors: Ruihua PENG, Monica Man Kay TANG, Xiaoling XU
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Publication number: 20210191737Abstract: A system for providing system level sleep state power savings includes a plurality of memory channels and corresponding plurality of memories coupled to respective memory channels. The system includes one or more processors operative to receive information indicating that a system level sleep state is to be entered and in response to receiving the system level sleep indication, moves data stored in at least a first of the plurality of memories to at least a second of the plurality of memories. In some implementations, in response to moving the data to the second memory, the processor causes power management logic to shut off power to: at least the first memory, to a corresponding first physical layer device operatively coupled to the first memory and to a first memory controller operatively coupled to the first memory and place the second memory in a self-refresh mode of operation.Type: ApplicationFiled: December 18, 2019Publication date: June 24, 2021Inventors: Jyoti Raheja, Hideki Kanayama, Guhan Krishnan, Ruihua Peng
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Publication number: 20180018221Abstract: In one form, a memory controller includes a command queue, an arbiter, and a replay queue. The command queue receives and stores memory access requests. The arbiter is coupled to the command queue for providing a sequence of memory commands to a memory channel. The replay queue stores the sequence of memory commands to the memory channel, and continues to store memory access commands that have not yet received responses from the memory channel. When a response indicates a completion of a corresponding memory command without any error, the replay queue removes the corresponding memory command without taking further action. When a response indicates a completion of the corresponding memory command with an error, the replay queue replays at least the corresponding memory command. In another form, a data processing system includes the memory controller, a memory accessing agent, and a memory system to which the memory controller is coupled.Type: ApplicationFiled: December 9, 2016Publication date: January 18, 2018Applicant: Advanced Micro Devices, Inc.Inventors: James R. Magro, Ruihua Peng, Anthony Asaro, Kedarnath Balakrishnan, Scott P. Murphy, YuBin Yao