Abstract: The invention provides a carrier frequency offset processing method, an apparatus and a receiver. The method comprises: receiving, through a software and hardware interface, an estimated value of frequency offset of a data packet transmitted by an automatic frequency offset control module; collecting the received estimated value of frequency offset of the data packet and performing statistical analysis to obtain a statistical value of carrier frequency offset between a receiving module and a transmitting module; and dynamically adjusting, according to the statistical value of carrier frequency offset, a bandwidth of a low-pass filter through the software and hardware interface. The invention realizes dynamic adjustment of the bandwidth of the low-pass filter in the process of a receiver receiving signals, solving the problem of the impact on processing performance brought by the fixed bandwidth of a low-pass filter in the prior art.

Abstract: A phase locked loop frequency calibration circuit and a method are provided. The circuit includes a timer, a counter, a control module, a frequency divider and a voltage controlled oscillator; output of voltage controlled oscillator is connected with first input of frequency divider, output of frequency divider is connected with first input of counter, second input of frequency divider, first input of timer and second input of counter are respectively connected with first output of control module, third input of counter is connected with output of timer, output of counter is connected with first input of control module, a reference clock signal is respectively sent to second input of timer and second input of control module, the number of clocks used by frequency divider to perform frequency division on output clock signal of voltage controlled oscillator is sent to third input of control module.

Abstract: A low noise amplifier and a chip. The amplifier includes a biasing circuit unit, a first amplifying circuit unit, a first adjusting unit, a first signal input, a second signal input and a first signal output; the biasing circuit unit includes a first voltage output and a second voltage output; the first amplifying circuit unit includes a first N-type transistor, a first P-type transistor, a first output capacitor, a second output capacitor, a first impedance and a second impedance; gates of first N-type and P-type transistors are connected to first voltage output and first signal input, and second voltage output and first signal input, respectively, via adjusting unit; source of first N-type transistor is connected to source of first P-type transistor and second signal input; drains of first N-type and P-type transistors are connected respectively to impedance, and to first signal output and second signal output via output capacitor.

Abstract: A phase locked loop frequency calibration circuit and a method are provided. The circuit includes a timer, a counter, a control module, a frequency divider and a voltage controlled oscillator; output of voltage controlled oscillator is connected with first input of frequency divider, output of frequency divider is connected with first input of counter, second input of frequency divider, first input of timer and second input of counter are respectively connected with first output of control module, third input of counter is connected with output of timer, output of counter is connected with first input of control module, a reference clock signal is respectively sent to second input of timer and second input of control module, the number of clocks used by frequency divider to perform frequency division on output clock signal of voltage controlled oscillator is sent to third input of control module.

Abstract: The invention provides a carrier frequency offset processing method, an apparatus and a receiver. The method comprises: receiving, through a software and hardware interface, an estimated value of frequency offset of a data packet transmitted by an automatic frequency offset control module; collecting the received estimated value of frequency offset of the data packet and performing statistical analysis to obtain a statistical value of carrier frequency offset between a receiving module and a transmitting module; and dynamically adjusting, according to the statistical value of carrier frequency offset, a bandwidth of a low-pass filter through the software and hardware interface. The invention realizes dynamic adjustment of the bandwidth of the low-pass filter in the process of a receiver receiving signals, solving the problem of the impact on processing performance brought by the fixed bandwidth of a low-pass filter in the prior art.

Abstract: A crystal oscillator, including: a voltage stabilizing unit, a transconductance unit, a feedback resistor, a crystal resonator and at least two ground capacitors. The voltage stabilizing unit includes a current source and a first branch circuit including PMOS and NMOS connected in series, PMOS has its source connected to output of the current source, PMOS and NMOS have their gates connected to drains thereof, and NMOS has its source connected to ground. The transconductance unit includes a second branch circuit including PMOS and NMOS connected in series, PMOS has its source connected to output of the voltage stabilizing unit, PMOS and NMOS have their gates connected to input of the crystal resonator and one end of the resistor, and have their drains connected to output of the crystal resonator and another end of the resistor. The capacitors are connected to two ends of the crystal resonator respectively and ground.

Abstract: A low noise amplifier and a chip. The amplifier includes a biasing circuit unit, a first amplifying circuit unit, a first adjusting unit, a first signal input, a second signal input and a first signal output; the biasing circuit unit includes a first voltage output and a second voltage output; the first amplifying circuit unit includes a first N-type transistor, a first P-type transistor, a first output capacitor, a second output capacitor, a first impedance and a second impedance; gates of first N-type and P-type transistors are connected to first voltage output and first signal input, and second voltage output and first signal input, respectively, via adjusting unit; source of first N-type transistor is connected to source of first P-type transistor and second signal input; drains of first N-type and P-type transistors are connected respectively to impedance, and to first signal output and second signal output via output capacitor.

Abstract: A crystal oscillator, including: a voltage stabilizing unit, a transconductance unit, a feedback resistor, a crystal resonator and at least two ground capacitors. The voltage stabilizing unit includes a current source and a first branch circuit including PMOS and NMOS connected in series, PMOS has its source connected to output of the current source, PMOS and NMOS have their gates connected to drains thereof, and NMOS has its source connected to ground. The transconductance unit includes a second branch circuit including PMOS and NMOS connected in series, PMOS has its source connected to output of the voltage stabilizing unit, PMOS and NMOS have their gates connected to input of the crystal resonator and one end of the resistor, and have their drains connected to output of the crystal resonator and another end of the resistor. The capacitors are connected to two ends of the crystal resonator respectively and ground.