Abstract: The present application discloses a dispatching and control cloud data processing method, device and system. The method includes the following operations: pilot node device acquires a global scheduling task, decomposes the global scheduling task to obtain scheduling tasks, issues the scheduling tasks to collaborative node device, acquires data collection ranges and data processing rules of the collaborative node devices, and delivers them to the collaborative node devices; the collaborative node devices receive and execute the scheduling tasks issued by the pilot node device; receives the data collection ranges and the data processing rules issued by the pilot node device, acquires, based on the scheduling tasks, collected data in the data collection ranges, processes the acquired collected data according to the data processing rules to obtain the processed data, uploads the processed data to the pilot node device; the pilot node device receives the processed data uploaded by the collaborative node devices.

Abstract: The present disclosure relates to a fractional frequency divider, a radio frequency transceiver, and a method of configuring a phase delay in the fractional frequency divider. The fractional frequency divider comprises a counter, a multiplexer, and a delay module. The method is applicable to the fractional frequency divider. The radio frequency transceiver comprises the fractional frequency divider, and the fractional frequency divider adopts the method. According to the aforesaid technical solution, the present disclosure has advantages as follows: the embodiments of the present disclosure can minimize the timing inaccuracy and suppress the output jitter and output spurs; and the embodiments of the present disclosure can effectively extend the operating frequency range of the fractional frequency divider.

Abstract: The present disclosure relates to a fractional frequency divider, a radio frequency transceiver, and a method of configuring a phase delay in the fractional frequency divider. The fractional frequency divider comprises a counter, a multiplexer, and a delay module. The method is applicable to the fractional frequency divider. The radio frequency transceiver comprises the fractional frequency divider, and the fractional frequency divider adopts the method. According to the aforesaid technical solution, the present disclosure has advantages as follows: the embodiments of the present disclosure can minimize the timing inaccuracy and suppress the output jitter and output spurs; and the embodiments of the present disclosure can effectively extend the operating frequency range of the fractional frequency divider.

Abstract: An operational amplifier, any of a pair of amplification circuits of its output-stage amplification circuit unit comprises: a first and second transistors, a capacitor and a DC bias circuit; a control electrode of the first transistor is connected with a corresponding output terminal of a preceding-stage amplification circuit unit, a first electrode thereof is connected with a first power terminal and a second electrode thereof is connected with an output terminal of an amplification circuit of the output-stage amplification circuit unit; an output terminal of the DC bias circuit is connected with a control electrode of the second transistor, a first electrode of which is connected with a second power terminal, and a second electrode thereof is connected with the output terminal; both ends of the capacitor are respectively connected with the control electrodes of the first and second transistors; and the first and second transistors are of opposite polarities.

Abstract: A deep neural network hardware accelerator comprises: an AXI-4 bus interface, an input cache area, an output cache area, a weighting cache area, a weighting index cache area, an encoding module, a configurable state controller module, and a PE array. The input cache area and the output cache area are designed as a line cache structure; an encoder encodes weightings according to an ordered quantization set, the quantization set storing the possible value of the absolute value of all of the weightings after quantization. During the calculation of the accelerator, the PE unit reads data from the input cache area and the weighting index cache area to perform shift calculation, and sends the calculation result to the output cache area. The accelerator uses shift operations to replace floating point multiplication operations, reducing the requirements for computing resources, storage resources, and communication bandwidth, and increasing the calculation efficiency of the accelerator.