Patents by Inventor Ruisheng Wu
Ruisheng Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11360737Abstract: The present disclosure discloses a method and apparatus for providing a speech service. A specific embodiment of the method comprises: receiving request information sent by a device, the request information comprising first event information and speech information, the first event information used for indicating a first event occurring on the device when the device sends the request information, wherein the first event information comprises speech input event information used for instructing a user to input the speech information; generating response information comprising an operation instruction for a targeted device on the basis of the first event information and the speech information; and sending the response information to the targeted device for the targeted device to perform an operation indicated by the operation instruction. The embodiment improves the efficiency of providing a speech service.Type: GrantFiled: July 5, 2018Date of Patent: June 14, 2022Assignee: BAIDU ONLINE NETWORK TECHNOLOGY (BEIJING) CO., LTDInventors: Jianliang Zhou, Guanghao Shen, Ruisheng Wu
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Patent number: 10839140Abstract: The present disclosure provides a page displaying method, device, apparatus based on an H5 webpage, and a computer readable storage medium. The page displaying method based on an H5 webpage includes: loading a main page in a webpage view; obtaining content of an H5 webpage; establishing a page tag, in which the page tag includes the content of the H5 webpage; and loading the page tag in the main page.Type: GrantFiled: March 26, 2019Date of Patent: November 17, 2020Assignee: BAIDU ONLINE NETWORK TECHNOLOGY (BEIJING) CO., LTD.Inventors: Hong Su, Peng Wang, Ruisheng Wu
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Publication number: 20190392025Abstract: The present disclosure provides a page displaying method, device, apparatus based on an H5 webpage, and a computer readable storage medium. The page displaying method based on an H5 webpage includes: loading a main page in a webpage view; obtaining content of an H5 webpage; establishing a page tag, in which the page tag includes the content of the H5 webpage; and loading the page tag in the main page.Type: ApplicationFiled: March 26, 2019Publication date: December 26, 2019Inventors: Hong SU, Peng WANG, Ruisheng WU
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Publication number: 20190012138Abstract: The present disclosure discloses a method and apparatus for providing a speech service. A specific embodiment of the method comprises: receiving request information sent by a device, the request information comprising first event information and speech information, the first event information used for indicating a first event occurring on the device when the device sends the request information, wherein the first event information comprises speech input event information used for instructing a user to input the speech information; generating response information comprising an operation instruction for a targeted device on the basis of the first event information and the speech information; and sending the response information to the targeted device for the targeted device to perform an operation indicated by the operation instruction. The embodiment improves the efficiency of providing a speech service.Type: ApplicationFiled: July 5, 2018Publication date: January 10, 2019Inventors: Jianliang ZHOU, Guanghao SHEN, Ruisheng WU
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Publication number: 20150340301Abstract: A vertical conductive power semiconductor device may include a substrate with a top metal layer located on a top surface of the substrate, solder bumps deposited on top of the top metal layer, and wafer level molding surrounding the solder bumps and leaving the solder bumps at least partly exposed.Type: ApplicationFiled: August 4, 2015Publication date: November 26, 2015Inventors: Tao Feng, Zhiqiang Niu, Yuping Gong, Ruisheng Wu, Ping Huang, Lei Shi, Yueh-Se Ho
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Patent number: 9136154Abstract: A substrate-less composite power semiconductor device may be fabricated from a vertical conductive power semiconductor device wafer that includes a top metal layer located on a top surface of the wafer by a) forming solder bumps on top of the top metal layer; b) forming wafer level molding around the solder bumps such that the solder bumps are exposed through a top of the wafer level molding; c) grinding a back side of the device wafer to reduce a total thickness of a semiconductor material portion of the device wafer to a final thickness; and d) forming a back metal on a back surface of the wafer.Type: GrantFiled: November 5, 2014Date of Patent: September 15, 2015Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Tao Feng, Zhiqiang Niu, Yuping Gong, Ruisheng Wu, Ping Huang, Lei Shi, Yueh-Se Ho
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Patent number: 8987878Abstract: A substrate-less composite power semiconductor device may include a thin substrate and a top metal layer located on a top surface of the substrate. A total thickness of the substrate and the epitaxial layer may be less than 25 microns. Solder bumps are formed on top of the top metal layer and molding compound surrounds the solder bumps and leaves the solder bumps at least partly exposed.Type: GrantFiled: October 29, 2010Date of Patent: March 24, 2015Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Tao Feng, Zhiqiang Niu, Yuping Gong, Ruisheng Wu, Ping Huang, Lei Shi, Yueh-Se Ho
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Publication number: 20150056752Abstract: A substrate-less composite power semiconductor device may be fabricated from a vertical conductive power semiconductor device wafer that includes a top metal layer located on a top surface of the wafer by a) forming solder bumps on top of the top metal layer; b) forming wafer level molding around the solder bumps such that the solder bumps are exposed through a top of the wafer level molding; c) grinding a back side of the device wafer to reduce a total thickness of a semiconductor material portion of the device wafer to a final thickness; and d) forming a back metal on a back surface of the wafer.Type: ApplicationFiled: November 5, 2014Publication date: February 26, 2015Inventors: Tao Feng, Zhiqiang Niu, Yuping Gong, Ruisheng Wu, Ping Huang, Lei Shi, Yueh-Se Ho
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Patent number: 8486803Abstract: A chip-scale packaging method, with bottom and side of a semiconductor chip encapsulated, includes the following steps: attaching backside of a thinned semiconductor wafer to a dicing tape; separating individual chips by cutting from front side of the wafer at scribe line but not cut through the dicing tape; flipping and attaching the wafer onto a top surface of a double-sided tape, then removing the dicing tape; attaching bottom surface of the double-sided tape on a supporting plate; filling the space between adjacent chips and covering the whole wafer backside with a molding material; flipping the whole structure and remove the supporting plate; placing solder balls at corresponding positions on electrodes of each chip and performing backflow treatment; finally separating individual chip packages by cutting through molding material at the space between adjacent chip packages with molding material encapsulating the bottom and side of each individual semiconductor chip.Type: GrantFiled: October 13, 2011Date of Patent: July 16, 2013Assignee: Alpha & Omega Semiconductor, Inc.Inventors: Ping Huang, Ruisheng Wu, Lei Duan, Yi Chen, Yuping Gong
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Publication number: 20130095612Abstract: A chip-scale packaging method, with bottom and side of a semiconductor chip encapsulated, includes the following steps: attaching backside of a thinned semiconductor wafer to a dicing tape; separating individual chips by cutting from front side of the wafer at scribe line but not cut through the dicing tape; flipping and attaching the wafer onto a top surface of a double-sided tape, then removing the dicing tape; attaching bottom surface of the double-sided tape on a supporting plate; filling the space between adjacent chips and covering the whole wafer backside with a molding material; flipping the whole structure and remove the supporting plate; placing solder balls at corresponding positions on electrodes of each chip and performing backflow treatment; finally separating individual chip packages by cutting through molding material at the space between adjacent chip packages with molding material encapsulating the bottom and side of each individual semiconductor chip.Type: ApplicationFiled: October 13, 2011Publication date: April 18, 2013Inventors: Ping Huang, Ruisheng Wu, Lei Duan, Yi Chen, Yuping Gong
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Publication number: 20120142165Abstract: A preparation process of wafer level chip scale packaging that prevents damaging a wafer in molding process is disclosed. In this process, a grinding grove is formed at a top side and around the edge of a wafer before molding is performed. The grinding groove effectively prevents the molding material from overflowing to the edge of the wafer, which avoids the damage of the wafer.Type: ApplicationFiled: March 10, 2011Publication date: June 7, 2012Inventors: Ping Huang, Ruisheng Wu, Yi Chen, Lei Duan, Wei Chen, Lihua Bao
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Publication number: 20120104580Abstract: A substrate-less composite power semiconductor device may include a thin substrate and a top metal layer located on a top surface of the substrate. A total thickness of the substrate and the epitaxial layer may be less than 25 microns. Solder bumps are formed on top of the top metal layer and molding compound surrounds the solder bumps and leaves the solder bumps at least partly exposed.Type: ApplicationFiled: October 29, 2010Publication date: May 3, 2012Applicant: Alpha and Omega Semiconductor IncorporatedInventors: Tao Feng, Zhiqiang Niu, Yuping Gong, Ruisheng Wu, Ping Huang, Lei Shi, Yueh-Se Ho
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Publication number: 20110294262Abstract: A semiconductor packaging process with improved die attach method for ultrathin chips package comprises the steps of providing a semiconductor wafer having a wafer frontside and a wafer backside with a plurality of integrated circuit chips (IC chips) formed on the wafer frontside; adhering a supporting substrate onto the wafer frontside through a bonding layer to form a wafer combo; grinding the wafer backside with the supporting substrate and the wafer bonded together; dicing the wafer combo into a plurality of die combos each comprising a substrate piece stacked on top of an IC chip bonded by a bonding layer piece; attaching a die combo onto a die pad of a lead frame with a bottom of the IC chip connected to the lead frame thereof; and removing the substrate piece with the bonding layer piece from the top surface of the IC chip.Type: ApplicationFiled: May 29, 2010Publication date: December 1, 2011Inventors: Ping Huang, Ruisheng Wu, Yi Chen, Lei Duan, Wei Chen, Lihua Bao
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Publication number: 20100327314Abstract: This invention discloses an IGBT device with its collector formed with Ge/Al and associated method of fabrication. The collector is formed on the substrate layer, which is on the back of IGBT, and contains Ge and Al thin films. After thinning and etching the back side of IGBT substrate, Ge and Al are sequentially deposited to form Ge/Al thin films on the back surface of the substrate. An annealing process is then carried out to diffuse Al into Ge thin film layer to form a P-doped Ge layer functioning as the IGBT collector. The present invention is applicable to both non punch through IGBTs as well as punch through IGBTs.Type: ApplicationFiled: June 28, 2009Publication date: December 30, 2010Inventors: Ping Huang, Tao Feng, Ruisheng Wu, Yi Chen, Lei Duan
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Patent number: 7842543Abstract: A wafer level chip scale package and method of laser marking the same are disclosed. The method includes forming a plurality of semiconductor devices on a frontside surface of a wafer, metallizing device contacts on the frontside surface of the wafer, grinding the backside surface of the wafer, silicon etching the backside surface of the wafer, laser marking the backside surface of the wafer following the silicon etch step, oxide etching the backside surface of the wafer following the laser marking step, depositing a metal layer on the backside surface of the wafer following the oxide etch step, and dicing the wafer into wafer level chip scale packages. A wafer level chip scale package includes a mark formed on a backside surface thereof, the mark comprising a plurality of trenches formed in a silicon backside surface and corresponding indentations formed in an overlaying back metal layer.Type: GrantFiled: February 17, 2009Date of Patent: November 30, 2010Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Ruisheng Wu, Yan Liu, Tao Feng
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Publication number: 20100207283Abstract: A wafer level chip scale package and method of laser marking the same are disclosed. The method includes forming a plurality of semiconductor devices on a frontside surface of a wafer, metallizing device contacts on the frontside surface of the wafer, grinding the backside surface of the wafer, silicon etching the backside surface of the wafer, laser marking the backside surface of the wafer following the silicon etch step, oxide etching the backside surface of the wafer following the laser marking step, depositing a metal layer on the backside surface of the wafer following the oxide etch step, and dicing the wafer into wafer level chip scale packages.Type: ApplicationFiled: February 17, 2009Publication date: August 19, 2010Inventors: Ruisheng Wu, Yan Liu, Tao Feng