Abstract: The repair systems and methods provide an application platform that has a downloadable application (UI) for mobile devices and a back-end dashboard for the manufacturers for assisting with repairs. The application program streamlines the entire repair journey from when an end-user needs to initiate a repair request until the repaired and re-certified device is shipped back by the manufacturer or repair facility to the end-user. The application may also provide end-users with the option to replace an unrepairable device or to perform a device swap.

Abstract: A method of determining a vehicle travel trajectory, an electronic device, a storage medium and a vehicle, which relate to a field of an artificial intelligence technology, in particular to a field of autonomous driving and intelligent transportation. A specific implementation solution includes: determining an initial path information for a vehicle; optimizing the initial path information to generate a target optimized path information; determining an optimized mapping relationship for velocity according to the target optimized path information and a first energy consumption constraint parameter; and determining an optimized trajectory for the vehicle according to the target optimized path information and the optimized mapping relationship for velocity.

Abstract: A mobile DR applicable to in-vivo detection of multi-thoracolumbar variations in equine animals and a use method are provided. The DR mainly comprises four aspects: (1) a digital flat-panel X-ray imaging system; (2) equine animal retaining device system (radiography bed) applicable to different body sizes; (3) radiography parameters applicable to equine animals of different body sizes and at different developmental stages; and (4) a stitching system Polaris for radiographed pictures. The digital flat-panel X-ray imaging system comprises an X-ray tube, a beam limiting device, a high-voltage generator, a flat-panel detector, an image acquisition workstation.

Abstract: The present invention provides a device and method for correcting error estimation of an analog-to-digital converter.

Abstract: A method for an analog-to-digital converter correcting error estimation includes: according to a correction parameter preset initial value, generating a control signal and finely tuning a digital control delay cell, adjusting a delay amount, and correcting a clock phase error between channels; according to a correction parameter initial value, correcting a gain error between channels, generating and buffering a general correction signal, and triggering a counting cell to start counting, and calling the general correction signal in a buffer and generating a preliminary estimation result by using a cyclic correlation method; when counting to a preset value, setting low-pass filter accumulating cell enable ends and a correction parameter updating cell, generating an error estimation result from the preliminary estimation result and latching it, updating a clock correction parameter and a gain correction parameter according to a gradient descent method, and latching them, and resetting to carry out cyclic estimat

Abstract: On-chip decoupling capacitor structures, and methods of fabricating such decoupling capacitors are disclosed. On-chip decoupling capacitors help to reduce or prevent L di/dt voltage droop on the power grid for high surge current conditions. The inclusion of one or more decoupling capacitors on a chip, in close proximity to the power grid conductors reduces parasitic inductance and thereby provides improved decoupling performance with respect to high frequency noise. In one embodiment of the present invention, a capacitor stack structure is inserted between metal interconnect layers. Such a capacitor stack may consist of a bottom electrode/barrier; a thin dielectric material having a high dielectric constant; and a top electrode/barrier. In an alternative embodiment, the bottom electrode and/or bottom metal interconnect layer have three dimensional texture to increase the surface area of the capacitor.

Abstract: An improvement in the method of fabricating on chip decoupling capacitors which help prevent L di/dt voltage droop on the power grid for high surge current conditions is disclosed. The inclusion of a hybrid metal/metal nitride top electrode/barrier provides for a low cost and higher performance option to strapping decoupling capacitors.

Abstract: The present invention discloses a method including: providing a silicon wafer; forming a buried oxide (BOX) in the silicon wafer below a silicon body; and reducing a thickness of the silicon body by chemical thinning.

Abstract: An improvement in the method of fabricating on chip decoupling capacitors which help prevent L di/dt voltage droop on the power grid for high surge current conditions is disclosed. The inclusion of a hybrid metal/metal nitride top electrode/barrier provides for a low cost and higher performance option to strapping decoupling capacitors.

Abstract: An improvement in the method of fabricating on chip decoupling capacitors which help prevent L di/dt voltage droop on the power grid for high surge current conditions is disclosed. The inclusion of a hybrid metal/metal nitride top electrode/barrier provides for a low cost and higher performance option to strapping decoupling capacitors.

Abstract: A layer transfer technique in which a portion of a donor wafer is doped with positively charged hydrogen ions and positively charged helium ions before it is bonded to a portion of a handle wafer. Furthermore, the bonded wafers are annealed at one of two annealing temperatures, which determines whether the wafers are separated using a thermal cleave or a mechanical cleave process.

Abstract: On-chip decoupling capacitor structures, and methods of fabricating such decoupling capacitors are disclosed. On-chip decoupling capacitors help to reduce or prevent L di/dt voltage droop on the power grid for high surge current conditions. The inclusion of one or more decoupling capacitors on a chip, in close proximity to the power grid conductors reduces parasitic inductance and thereby provides improved decoupling performance with respect to high frequency noise. In one embodiment of the present invention, a capacitor stack structure is inserted between metal interconnect layers. Such a capacitor stack may consist of a bottom electrode/barrier; a thin dielectric material having a high dielectric constant; and a top electrode/barrier. In an alternative embodiment, the bottom electrode and/or bottom metal interconnect layer have three dimensional texture to increase the surface area of the capacitor.

Abstract: On-chip decoupling capacitor structures, and methods of fabricating such decoupling capacitors are disclosed. On-chip decoupling capacitors help to reduce or prevent L di/dt voltage droop on the power grid for high surge current conditions. The inclusion of one or more decoupling capacitors on a chip, in close proximity to the power grid conductors reduces parasitic inductance and thereby provides improved decoupling performance with respect to high frequency noise. In one embodiment of the present invention, a capacitor stack structure is inserted between metal interconnect layers. Such a capacitor stack may consist of a bottom electrode/barrier; a thin dielectric material having a high dielectric constant; and a top electrode/barrier. In an alternative embodiment, the bottom electrode and/or bottom metal interconnect layer have three dimensional texture to increase the surface area of the capacitor.

Abstract: The present invention discloses a method including: providing a silicon wafer; forming a buried oxide (BOX) in the silicon wafer below a silicon body; and reducing a thickness of the silicon body by chemical thinning.

Abstract: The present invention discloses a method including: providing a silicon wafer; forming a buried oxide (BOX) in the silicon wafer below a silicon body; and reducing a thickness of the silicon body by chemical thinning.

Abstract: A layer transfer technique in which a portion of a donor wafer is doped with positively charged hydrogen ions and positively charged helium ions before it is bonded to a portion of a handle wafer. Furthermore, the bonded wafers are annealed at one of two annealing temperatures, which determines whether the wafers are separated using a thermal cleave or a mechanical cleave process.

Abstract: The present invention discloses a method including: providing a silicon wafer; forming a buried oxide (BOX) in the silicon wafer below a silicon body; and reducing a thickness of the silicon body by chemical thinning.

Abstract: On-chip decoupling capacitor structures, and methods of fabricating such decoupling capacitors are disclosed. On-chip decoupling capacitors help to reduce or prevent L di/dt voltage droop on the power grid for high surge current conditions. The inclusion of one or more decoupling capacitors on a chip, in close proximity to the power grid conductors reduces parasitic inductance and thereby provides improved decoupling performance with respect to high frequency noise. In one embodiment of the present invention, a capacitor stack structure is inserted between metal interconnect layers. Such a capacitor stack may consist of a bottom electrode/barrier; a thin dielectric material having a high dielectric constant; and a top electrode/barrier. In an alternative embodiment, the bottom electrode and/or bottom metal interconnect layer have three dimensional texture to increase the surface area of the capacitor.

Abstract: On-chip decoupling capacitor structures, and methods of fabricating such decoupling capacitors are disclosed. In one embodiment of the present invention, a capacitor stack may consist of a bottom electrode/barrier; a thin dielectric material having a high dielectric constant; and a top electrode/barrier. In an alternative embodiment, the bottom electrode and/or bottom metal interconnect layer have three dimensional texture to increase the surface area of the capacitor. An illustrative method embodying the present invention, includes fabricating the on-chip decoupling capacitor stack structure and electrically connecting the capacitor to provide efficient capacitive de-coupling.

Abstract: An improvement in the method of fabricating on chip decoupling capacitors which help prevent L di/dt voltage droop on the power grid for high surge current conditions is disclosed. The inclusion of a hybrid metal/metal nitride top electrode/barrier provides for a low cost and higher performance option to strapping decoupling capacitors.