Abstract: Embodiments of the present disclosure include a thinned device structure and method of forming a thinned device structure. Embodiments of the disclosure provided herein include the use of engineered epitaxial (Epi) layers that are formed on a base substrate. The engineered epitaxial layers include two or more epitaxial layers that each include materials that allow at least one of the two or more epitaxial layers to be selectively removed from the other layer(s). In some embodiments, one of the two or more formed epitaxial layers has etch selectivity (e.g., wet and/or dry etch selectivity) to materials disposed on either side of the formed layer.

Abstract: A method includes obtaining, by a processing device, first image data of a substrate including an epitaxial film. The method further includes applying a frequency domain filter to the first image data to obtain filtered image data. The method further includes determining a number of epitaxial defects represented in the first image data by performing feature detection on the filtered image data. The method further includes performing a corrective action in view of the number of epitaxial defects.

Abstract: Three-dimensional (3D) memory structures and methods of formation of same are provided herein. In some embodiments, a 3D memory fabrication structure includes: a base silicon (Si) layer; a silicon germanium (SiGe) layer disposed above the base Si layer; and a doped silicon (Si) layer disposed on at least one side of the SiGe layer, wherein the doped Si layer contains a dopant that is at least one of carbon (C) or boron (B).

Abstract: A semiconductor device and a method for manufacturing thereof. A substrate is provided. One or more groups of layers are formed on top of the substrate. A compensation layer is formed on top of at least one group of layers. At least one silicon layer is formed on top of the compensation layer. At least a portion of one or more layers in the one or more groups of layers is etched. The semiconductor device is formed.

Abstract: A semiconductor device and a method for manufacturing thereof. A substrate is provided. At least one silicon layer is formed on top of the substrate. At least one silicon-germanium layer is formed on top of at least one silicon layer. At least one silicon-germanium layer includes at least one n-type dopant. The semiconductor device having at least one silicon layer and at least one silicon-germanium layer is formed.

Abstract: Embodiments of the present disclosure generally relate to methods for providing real-time characterization of photoresist properties. In some embodiments, a method of preparing a patterned photoresist on a substrate includes forming an unpatterned photoresist on the substrate, exposing the unpatterned photoresist to a first dose of EM radiation at a first location on the unpatterned photoresist with a first light source, and measuring an optical property of the unpatterned photoresist and exposing the unpatterned photoresist to a second dose of EM radiation at the first location on the unpatterned photoresist to create a patterned or partially patterned photoresist. The second dose of EM radiation has a greater wavelength, a greater number of pulses, or a longer exposure period than the first dose of EM radiation with a second light source. Also, at least one of the first light source and the second light source is an on-board metrology device.

Abstract: Embodiments disclosed herein include a method of forming a metal-oxo photoresist on a substrate. In an embodiment, the method comprises repeating a deposition cycle, where each iteration of the deposition cycle comprises: a) flowing a metal precursor into a chamber comprising the substrate; and b) flowing an oxidant into the chamber, where the oxidant and the metal precursor react to form the metal-oxo photoresist.

Abstract: Embodiments of the present invention may include single crystal silicon solar cell structures with epitaxially deposited silicon device layers with deep junction(s). In some embodiments, the single crystal silicon solar cell structures may comprise a moderately doped, thick (greater than 10 microns), epitaxially deposited silicon emitter layer. In some embodiments, the single crystal silicon solar cell structures may comprise moderately doped, thick (greater than 10 microns), epitaxially deposited FSF layers. The moderate doping reduces electron-hole recombination within the FSF and emitter layers and causes smaller bandgap narrowing and reduced Auger recombination compared to prior art devices which typically have more heavily doped layers, and the thicker FSF and emitter layers than typically used in prior art devices assist in having a desirable sheet resistance for the solar cell front and back surface, as measured prior to front side and back side metallization.

Abstract: High efficiency silicon solar cells, including IBC cells, may be formed from lightly doped p-n sandwich structures fabricated in-situ by epitaxial growth. For example, the solar cell may comprise: an n-type silicon layer greater than or equal to 20 microns thick, with a dopant concentration between 1E15/cm3 and 5E16/cm3 and a bulk silicon carrier lifetime greater than 50 microseconds; a p-type silicon layer greater than 10 microns thick, with a dopant concentration between 1E16/cm3 and 5E18/cm3, and a bulk silicon carrier lifetime greater than 10 microseconds; wherein the n-type and p-type silicon layers were fabricated by epitaxial deposition, one after the other, on a reusable single crystal silicon substrate. The ideality factor of the silicon solar cell may be approximately 1.0. The epitaxial deposition may be in a reactor with low auto-doping and low oxygen incorporation.