Abstract: Embodiments disclosed herein include a semiconductor processing tool. In an embodiment, the semiconductor processing tool comprises a pedestal, an annular separator over the pedestal to define a first domain within the annular separator and a second domain outside of the annular separator, a first gas inlet within the annular separator, and a second gas inlet outside of the annular separator.

Abstract: Embodiments disclosed herein include a method of monitoring a photoresist deposition process. In an embodiment, the method comprises depositing a photoresist layer to a first thickness over a substrate, measuring a property of the photoresist layer with a first electromagnetic (EM) radiation source, depositing the photoresist layer to a second thickness over the substrate, and measuring the property of the photoresist layer with the first EM radiation source.

Abstract: Embodiments disclosed herein include a method of optimizing a post deposition bake of a photoresist layer. In an embodiment, the method comprises depositing the photoresist layer on a substrate, baking the photoresist layer, and measuring properties of the photoresist layer with an optical tool.

Abstract: Embodiments of the present disclosure generally relate to methods for providing real-time characterization of photoresist properties. In some embodiments, a method of preparing a patterned photoresist on a substrate includes forming an unpatterned photoresist on the substrate, exposing the unpatterned photoresist to a first dose of EM radiation at a first location on the unpatterned photoresist with a first light source, and measuring an optical property of the unpatterned photoresist and exposing the unpatterned photoresist to a second dose of EM radiation at the first location on the unpatterned photoresist to create a patterned or partially patterned photoresist. The second dose of EM radiation has a greater wavelength, a greater number of pulses, or a longer exposure period than the first dose of EM radiation with a second light source. Also, at least one of the first light source and the second light source is an on-board metrology device.

Abstract: Embodiments include a gas distribution assembly for a semiconductor processing chamber. In an embodiment, the gas distribution assembly comprises a flow ratio controller (FRC). In an embodiment, a first line from the FRC goes to an ampoule, and a second line from the FRC goes to a main line. In an embodiment, a third line from the ampoule goes to the main line. In an embodiment, a mass flow meter is coupled to the main line.

Abstract: Embodiments disclosed herein include methods for removing a metal containing layer from a chamber of a tool. In an embodiment, the method comprises generating a remote plasma in the tool. The method may continue with flowing reactive species from the remote plasma into the chamber, and flowing a hydrocarbon gas into the chamber. In an embodiment, the method may include reacting the reactive species with the hydrocarbon gas within the chamber. In an embodiment, the method may further comprise etching the metal-containing material in the chamber.

Abstract: Embodiments disclosed herein include a method of forming a metal-oxo photoresist on a substrate. In an embodiment, the method comprises repeating a deposition cycle, where each iteration of the deposition cycle comprises: a) flowing a metal precursor into a chamber comprising the substrate; and b) flowing an oxidant into the chamber, where the oxidant and the metal precursor react to form the metal-oxo photoresist.

Abstract: Embodiments of the present invention may include single crystal silicon solar cell structures with epitaxially deposited silicon device layers with deep junction(s). In some embodiments, the single crystal silicon solar cell structures may comprise a moderately doped, thick (greater than 10 microns), epitaxially deposited silicon emitter layer. In some embodiments, the single crystal silicon solar cell structures may comprise moderately doped, thick (greater than 10 microns), epitaxially deposited FSF layers. The moderate doping reduces electron-hole recombination within the FSF and emitter layers and causes smaller bandgap narrowing and reduced Auger recombination compared to prior art devices which typically have more heavily doped layers, and the thicker FSF and emitter layers than typically used in prior art devices assist in having a desirable sheet resistance for the solar cell front and back surface, as measured prior to front side and back side metallization.

Abstract: High efficiency silicon solar cells, including IBC cells, may be formed from lightly doped p-n sandwich structures fabricated in-situ by epitaxial growth. For example, the solar cell may comprise: an n-type silicon layer greater than or equal to 20 microns thick, with a dopant concentration between 1E15/cm3 and 5E16/cm3 and a bulk silicon carrier lifetime greater than 50 microseconds; a p-type silicon layer greater than 10 microns thick, with a dopant concentration between 1E16/cm3 and 5E18/cm3, and a bulk silicon carrier lifetime greater than 10 microseconds; wherein the n-type and p-type silicon layers were fabricated by epitaxial deposition, one after the other, on a reusable single crystal silicon substrate. The ideality factor of the silicon solar cell may be approximately 1.0. The epitaxial deposition may be in a reactor with low auto-doping and low oxygen incorporation.