Patents by Inventor Rumiko Ichitani, legal representative

Rumiko Ichitani, legal representative has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device
    Patent number: 7615872
    Abstract: A semiconductor device comprises: a package substrate having a plurality of bonding electrodes arranged in a peripheral region of a main surface thereof and wirings connected to the respective bonding electrodes and electrolessly plated; a semiconductor chip mounted on the package substrate; a plurality of wires connecting pads of the semiconductor chip and the bonding electrodes; a sealing body for sealing the semiconductor chip and the wires with resin; and a plurality of solder balls arranged on the package substrate. The wirings are formed only at the inner side of the plurality of bonding electrodes on the main surface of the package substrate, and no solder resist film is formed at the outer side of the plurality of bonding electrodes. With this arrangement, the region outside the bonding electrodes can be minimized and the semiconductor device can be downsized without changing the size of the chip mounted thereon.
    Type: Grant
    Filed: December 5, 2008
    Date of Patent: November 10, 2009
    Assignees: Renesas Technology Corp., Renesas Northern Japan Semiconductor, Inc.
    Inventors: Noriyuki Takahashi, Masahiro Ichitani, Rumiko Ichitani, legal representative, Kazuhiro Ichitani, legal representative, Sachiyo Ichitani, legal representative
  • Semiconductor device
    Patent number: 7479705
    Abstract: A semiconductor device comprises: a package substrate having a plurality of bonding electrodes arranged in a peripheral region of a main surface thereof and wirings connected to the respective bonding electrodes and electrolessly plated; a semiconductor chip mounted on the package substrate; a plurality of wires connecting pads of the semiconductor chip and the bonding electrodes; a sealing body for sealing the semiconductor chip and the wires with resin; and a plurality of solder balls arranged on the package substrate. The wirings are formed only at the inner side of the plurality of bonding electrodes on the main surface of the package substrate, and no solder resist film is formed at the outer side of the plurality of bonding electrodes. With this arrangement, the region outside the bonding electrodes can be minimized and the semiconductor device can be downsized without changing the size of the chip mounted thereon.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: January 20, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Noriyuki Takahashi, Rumiko Ichitani, legal representative, Kazuhiro Ichitani, legal representative, Sachiyo Ichitani, legal representative, Masahiro Ichitani