Patents by Inventor Rumin JI
Rumin JI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230020078Abstract: Provided is an anti-fuse memory circuit. The anti-fuse memory circuit includes a memory array, a bit line (BL), and a word line (WL); an anti-fuse memory cell (FsBIn) electrically connected to the bit line (BL) through a first switch transistor (1Add); a second switch transistor (2Add) configured to connect the bit line (BL) to a transmission wire (100); a third switch transistor (3Add) configured to discharge the transmission wire (100); a reading module (102) including a first input end (+) connected to the transmission wire (100), a second input end (?) for receiving a reference voltage (VTRIP), and a sampling input end (C) for receiving a sampling signal (CLK); and a compensation module (101), connected to the third switch transistor (3Add) and configured to slow down a drop speed of a voltage at the transmission wire (100).Type: ApplicationFiled: January 10, 2022Publication date: January 19, 2023Inventor: Rumin JI
-
Publication number: 20230012334Abstract: An anti-fuse memory circuit includes: a memory array including multiple anti-fuse memory cells; bit lines, each connected to the anti-fuse memory cells arranged in extension direction of the bit line, each anti-fuse memory cell being electrically connected to respective one of bit lines through first switch transistor; word lines, each connected to first switch transistors arranged in extension direction of word line; a second switch transistor connects one of the bit lines to transmission wire; a reading circuit, having first input terminal connected to the transmission wire, second input terminal for receiving reference voltage, and sampling input terminal for receiving sampling signal; and a signal generation circuit for generating sampling signal according to precharge voltage and precharge signal, where precharge signal is used for instructing to precharge transmission wire to precharge voltage, and delay duration between sampling signal and precharge signal is positively correlated with voltage amplitudType: ApplicationFiled: February 18, 2022Publication date: January 12, 2023Inventor: Rumin JI
-
Publication number: 20220311429Abstract: A comparator includes a first-stage op amp circuit, a second-stage op amp circuit, a bias circuit and a clamping circuit. The first-stage op amp circuit includes two voltage input terminals and a voltage output terminal; the second-stage op amp circuit is connected with the bias circuit and the voltage output terminal of the first-stage op amp circuit; and the clamping circuit is connected with the voltage output terminal of the first-stage op amp circuit. By adding a clamping circuit in the comparator, the highest voltage at the voltage output terminal of the first-stage op amp circuit can be clamped to a preset voltage. During the operation of the comparator, the voltage change range of the voltage output terminal of the first-stage op amp circuit is smaller, which reduces the discharge delay of the voltage output terminal of the first-stage op amp circuit, thereby increasing the flip speed of the comparator.Type: ApplicationFiled: June 19, 2020Publication date: September 29, 2022Inventor: Rumin Ji
-
Patent number: 11393521Abstract: A power module and a memory device are disclosed. The power module includes: a voltage raise unit for outputting a power voltage; an enabling unit connected to the power output for generating and outputting an enabling signal; a control unit, includes: an oscillator, a pulse generator, and an OR operation unit; the oscillator generates a delayed pulse control signal with a certain period; the pulse generator connects to the output terminal of the enabling unit for receiving the enable signal, synchronously generates an instant pulse control signal; the OR operation unit performs OR calculation to the delay pulse control signal and the instant pulse control signal to generate a boost control signal. The output end of the control unit connects to the voltage raise unit, and outputs the boost control signal to the voltage raise unit. The above-mentioned power module has a high transient response capability and maintains the stability of the output power voltage.Type: GrantFiled: February 22, 2020Date of Patent: July 19, 2022Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Rumin Ji
-
Publication number: 20220148628Abstract: The disclosure provides a sense amplifier and a control method thereof. The sense amplifier includes: a pre-charge module, a first input and output terminal, a second input and output terminal, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor, a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a fifth switch unit, a sixth switch unit, a seventh switch unit, an eighth switch unit, a first energy storage unit and a second energy storage unit. The sense amplifier can compensate for the offset voltage. The result is a sense amplifier with greatly reduced offset voltage, thereby improving the sensitivity and resolution of the sense amplifier.Type: ApplicationFiled: June 19, 2020Publication date: May 12, 2022Inventor: Rumin JI
-
Publication number: 20220130448Abstract: A state detection circuit for an anti-fuse memory cell includes: amplifier, having first input terminal connected with first reference voltage, second input terminal connected with first node and output terminal connected with second node; anti-fuse memory cell array, including anti-fuse memory cell sub-arrays, bit lines of sub-arrays are connected with first node, word lines of sub-arrays are connected with controller and each sub-array includes anti-fuse memory cells; first switch element, having first terminal connected with power supply, second terminal connected with first node and control terminal connected with second node; second switch element, having first terminal connected with power supply, second terminal connected with third node and control terminal connected with second node; third switch element, having first terminal connected with third node, grounded second terminal and control terminal connected with controller; and comparator, having first and second input terminals connected with thirdType: ApplicationFiled: January 7, 2022Publication date: April 28, 2022Inventor: Rumin JI
-
Publication number: 20220115053Abstract: A power module and a memory device are disclosed. The power module includes: a voltage raise unit for outputting a power voltage; an enabling unit connected to the power output for generating and outputting an enabling signal; a control unit, includes: an oscillator, a pulse generator, and an OR operation unit; the oscillator generates a delayed pulse control signal with a certain period; the pulse generator connects to the output terminal of the enabling unit for receiving the enable signal, synchronously generates an instant pulse control signal; the OR operation unit performs OR calculation to the delay pulse control signal and the instant pulse control signal to generate a boost control signal. The output end of the control unit connects to the voltage raise unit, and outputs the boost control signal to the voltage raise unit. The above-mentioned power module has a high transient response capability and maintains the stability of the output power voltage.Type: ApplicationFiled: February 22, 2020Publication date: April 14, 2022Inventor: Rumin Ji
-
Publication number: 20220077821Abstract: An oscillating circuit comprises a constant voltage supply circuit, a constant current supply circuit and an oscillating circuit; the constant voltage supply circuit is configured to output constant voltage; the constant current supply circuit is configured to output constant current; and the oscillating circuit is connected to the constant voltage supply circuit and the constant current supply circuit, and is configured to generate an oscillating signal with a preset frequency according to the constant voltage and the constant current.Type: ApplicationFiled: September 20, 2021Publication date: March 10, 2022Inventors: Rumin JI, Haining XU
-
Publication number: 20220074978Abstract: A voltage detection circuit and a charge pump circuit using the voltage detection circuit are provided. The voltage detection circuit includes: a voltage raising circuit configured to adjust a voltage to be measured and then output an adjusted voltage, where the adjusted voltage is equal to the sum of the voltage to be measured and a reference voltage; and the reference voltage is generated by a combination of a first voltage with a positive temperature coefficient and a second voltage with a negative temperature coefficient.Type: ApplicationFiled: September 9, 2021Publication date: March 10, 2022Inventor: Rumin JI
-
Publication number: 20220020443Abstract: A state detection circuit of an anti-fuse memory cell includes a first switching element, having a first end connected to a power supply, a second end connected to a first node, and a control end connected to a controller; an anti-fuse memory cell array including a plurality of anti-fuse memory cell sub-arrays, bit lines of the plurality of anti-fuse memory cell sub-arrays being all connected to the first node, and word lines of the plurality of anti-fuse memory cell sub-arrays being all connected to the controller; and a comparator, having a first input end connected to the first node, and a second input end connected to a reference voltage.Type: ApplicationFiled: August 27, 2021Publication date: January 20, 2022Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Rumin JI
-
Publication number: 20220020444Abstract: A circuit for detecting a state of an anti-fuse storage unit includes a first current module, a second current module, and a comparator. The first current module has a first end connected to an anti-fuse storage unit array through a first node and a second end connected to a second node. The first current module is configured to output a detection current through the second node. The second current module has a first end connected to a first end of a reference resistor through a third node and a second end connected to a fourth node. A second end of the reference resistor is grounded. The second current module is configured to output a reference current through the fourth node. The comparator has a first input end connected to the second node and a second input end connected to the fourth node.Type: ApplicationFiled: August 12, 2021Publication date: January 20, 2022Inventor: Rumin JI
-
Publication number: 20220020442Abstract: A circuit for detecting an anti-fuse memory cell state includes a current providing module connected to a first node and used to provide constant current; an anti-fuse memory cell array connected to the first node and including at least one bit line, the at least one bit line is connected to a plurality of anti-fuse memory cells and the first node; and a comparator, a first input end of the comparator is connected to the first node and a second input end of the comparator is connected to a first reference voltage, and used to detect a storage state of an anti-fuse memory cell to be tested in the anti-fuse memory cell array.Type: ApplicationFiled: August 18, 2021Publication date: January 20, 2022Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Rumin JI
-
Publication number: 20210208618Abstract: Embodiment provides an on-chip reference current generating circuit for supplying at least one reference current to at least one load. The on-chip reference current generating circuit includes a transistor, an operational amplifier unit, a first pull-down resistor unit, and a current mirror unit. A reference voltage is inputted to a positive input terminal of the operational amplifier unit, a negative input terminal of the operational amplifier unit is coupled to a source of the transistor, and an output terminal of the operational amplifier unit is coupled to a gate of the transistor. As a resistor unit calibrated by a ZQ calibration circuit, the first pull-down resistor unit is coupled between the source of the transistor and a ground. The current mirror unit is coupled between a drain of the transistor and a power supply voltage and is configured to output a generated current to the load for use.Type: ApplicationFiled: March 3, 2021Publication date: July 8, 2021Inventors: Rumin JI, Zhan YING