Patents by Inventor Runshun Wang
Runshun Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230343639Abstract: An etch stop detection structure and an etch stop detection method are provided. The etch stop detection structure includes a substrate, a first dielectric layer, a first stop layer, and a second dielectric layer. The substrate includes a device region and a detection region. The first dielectric layer is located on the substrate. The first stop layer is located on the first dielectric layer. The second dielectric layer is located on the first stop layer. There is a first air gap in the first dielectric layer and the first stop layer in the device region. There is a trench in the second dielectric layer in the detection region. The trench exposes the first stop layer. The etch stop detection structure can be used to detect the etch stop signal.Type: ApplicationFiled: May 19, 2022Publication date: October 26, 2023Applicant: United Microelectronics Corp.Inventors: Runshun Wang, Mengkai Zhu, Zhuona Ma, Hua-Kuo Lee
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Publication number: 20230058468Abstract: A method of fabricating an air gap includes receiving a first thickness information of an inter-metal dielectric layer formed on a substrate and receiving a second thickness information of an inter-layer dielectric layer formed on the substrate. Then, a first etching is performed, wherein the first etching includes etch the inter-metal dielectric layer based on a first etching control value corresponding to the first thickness information. After the first etching, a second etching is performed to etch the inter-layer dielectric layer based on a second etching control value corresponding to the second thickness information.Type: ApplicationFiled: August 23, 2021Publication date: February 23, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: BO TAO, RUNSHUN WANG, Li Wang, Ching-Yang Wen, Purakh Raj Verma, DONG YIN, Jian Xie
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Patent number: 11417735Abstract: A method for fabricating a semiconductor device is provided. The method includes providing a substrate, having a cell region and a logic region and including a first conductive layer as a top layer, wherein shallow trench isolation (STI) structures are disposed in the substrate at cell region and the logic region. A first dry etching process is performed to preliminarily etch the first conductive layer and the STI structures at the cell region. A wet etching process is performed over the substrate to etch the STI structures down to a preserved height. A control gate stack is formed on the first conductive layer at the cell region. A second dry etching process is performed on a portion of the first conductive layer to form a floating gate under the control gate stack at the cell region and remove the first conductive layer at the logic region.Type: GrantFiled: March 27, 2020Date of Patent: August 16, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Zhuona Ma, Mengkai Zhu, Runshun Wang, Hua-Kuo Lee
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Publication number: 20210305377Abstract: A method for fabricating a semiconductor device is provided. The method includes providing a substrate, having a cell region and a logic region and including a first conductive layer as a top layer, wherein shallow trench isolation (STI) structures are disposed in the substrate at cell region and the logic region. A first dry etching process is performed to preliminarily etch the first conductive layer and the STI structures at the cell region. A wet etching process is performed over the substrate to etch the STI structures down to a preserved height. A control gate stack is formed on the first conductive layer at the cell region. A second dry etching process is performed on a portion of the first conductive layer to form a floating gate under the control gate stack at the cell region and remove the first conductive layer at the logic region.Type: ApplicationFiled: March 27, 2020Publication date: September 30, 2021Applicant: United Microelectronics Corp.Inventors: ZHUONA MA, Mengkai Zhu, Runshun Wang, Hua-Kuo Lee
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Publication number: 20210020696Abstract: The invention discloses a structure of a memory device. The structure includes a substrate, having a memory region and a logic region. A barrier layer is disposed on the substrate, covering the memory region and the logic region. A patterned inter-layer dielectric layer is disposed on the barrier layer only at the memory region. A first via structure is formed in the barrier layer and the patterned inter-layer dielectric layer at the memory region. A memory cell structure is disposed on the patterned inter-layer dielectric layer at the memory region, in contact with the first via structure. An interconnection structure is disposed on the barrier layer at the logic region.Type: ApplicationFiled: August 12, 2019Publication date: January 21, 2021Applicant: United Microelectronics Corp.Inventors: Runshun Wang, Mengkai Zhu, Zhuona Ma, Hua-Kuo Lee
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Patent number: 10727234Abstract: The present invention provides a layout of a semiconductor transistor device including a first and a second active area, a first and a second gate, and a metal line. The first active and the second active area are extended along a first direction. The first gate and the second gate are extended along a second direction and crossed the first active area, to define two transistors. The two transistors are electrically connected with each other through a conductive layer. The metal line is disposed on the conductive layer and is electrically connected the two transistors respectively.Type: GrantFiled: November 27, 2016Date of Patent: July 28, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Zhibiao Zhou, Ding-Lung Chen, Xing Hua Zhang, Shan Liu, Runshun Wang, Chien-Fu Chen, Wei-Jen Wang, Chen-Hsien Hsu
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Publication number: 20180151571Abstract: The present invention provides a layout of a semiconductor transistor device including a first and a second active area, a first and a second gate, and a metal line. The first active and the second active area are extended along a first direction. The first gate and the second gate are extended along a second direction and crossed the first active area, to define two transistors. The two transistors are electrically connected with each other through a conductive layer. The metal line is disposed on the conductive layer and is electrically connected the two transistors respectively.Type: ApplicationFiled: November 27, 2016Publication date: May 31, 2018Inventors: ZHIBIAO ZHOU, Ding-Lung Chen, Xing Hua Zhang, Shan Liu, RUNSHUN WANG, Chien-Fu Chen, Wei-Jen Wang, Chen-Hsien Hsu
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Patent number: 7598179Abstract: Techniques for removal of photolithographic films used in the manufacture of semiconductor devices are provided. A substrate support member of a first processing chamber includes at least three retractable pins capable of elevating a wafer from a surface of the substrate support member. In addition, the first processing chamber is configured to automatically maintain the substrate support member at a first temperature. The wafer is elevated from the surface of the substrate support member using the at least three retractable pins. Thermal heating of the substrate from the substrate support member is reduced. A photoresist layer of the substrate is etched away while the substrate is in an elevated position. An anti-reflective layer of the substrate can be etched to remove substantially all of the anti-reflective layer. In a specific embodiment, the anti-reflective layer includes a DUO™ Bottom Anti-Reflective Coating by Honeywell International Inc.Type: GrantFiled: October 4, 2005Date of Patent: October 6, 2009Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Runshun Wang, Chao Wang, Lien Huang Cheng
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Publication number: 20070072390Abstract: Techniques for removal of photolithographic films used in the manufacture of semiconductor devices are provided. A substrate support member of a first processing chamber includes at least three retractable pins capable of elevating a wafer from a surface of the substrate support member. In addition, the first processing chamber is configured to automatically maintain the substrate support member at a first temperature. The wafer is elevated from the surface of the substrate support member using the at least three retractable pins. Thermal heating of the substrate from the substrate support member is reduced. A photoresist layer of the substrate is etched away while the substrate is in an elevated position. An anti-reflective layer of the substrate can be etched to remove substantially all of the anti-reflective layer. In a specific embodiment, the anti-reflective layer includes a DUO™ Bottom Anti-Reflective Coating by Honeywell International Inc.Type: ApplicationFiled: October 4, 2005Publication date: March 29, 2007Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Runshun Wang, Chao Wang, Lien Cheng