Abstract: Examples are disclosed that relate to sensing a position of a surface proximate to a resonant LC sensor. One example provides a method on a sensing device comprising one or more resonant LC sensors each configured to output a signal responsive to a position of a surface proximate to the resonant LC sensor. The method comprises, for each LC sensor, generating an oscillating signal on an antenna of the resonant LC sensor and detecting a near-field response of the resonant LC sensor at a selected frequency.

Abstract: Examples are disclosed that relate to sensing a position of a surface proximate to a resonant LC sensor. One example provides a method on a sensing device comprising one or more resonant LC sensors each configured to output a signal responsive to a position of a surface proximate to the resonant LC sensor. The method comprises, for each LC sensor, generating an oscillating signal on an antenna of the resonant LC sensor and detecting a near-field response of the resonant LC sensor at a selected frequency.

Abstract: Examples are disclosed that relate to sensing a position of a surface proximate to a resonant LC sensor. One example provides a method on a sensing device comprising one or more resonant LC sensors each configured to output a signal responsive to a position of a surface proximate to the resonant LC sensor. The method comprises, for each LC sensor, generating an oscillating signal on an antenna of the resonant LC sensor and detecting a near-field response of the resonant LC sensor at a selected frequency.

Abstract: Embodiments are disclosed that relate to implementing semiconductor device cooling systems that leverage awareness of regional voltage and temperature reliability risk considerations. For example, one disclosed embodiment provides a method of implementing a cooling system configured to cool an integrated circuit. The method involves first determining a heat dissipation factor that would reduce each region of the integrated circuit to a reduced temperature in order to maintain an overall failure rate. An analysis is then performed, using an insight about the relative reliability risk of elevated voltage and temperatures, to identify a region of the integrated circuit whose temperature can be permitted to rise without exceeding the overall failure rate, thereby permitting implementation of a cooling system with a reduced heat dissipation factor.

Abstract: Embodiments are disclosed that relate to implementing semiconductor device cooling systems that leverage awareness of regional voltage and temperature reliability risk considerations. For example, one disclosed embodiment provides a method of implementing a cooling system configured to cool an integrated circuit. The method involves first determining a heat dissipation factor that would reduce each region of the integrated circuit to a reduced temperature in order to maintain an overall failure rate. An analysis is then performed, using an insight about the relative reliability risk of elevated voltage and temperatures, to identify a region of the integrated circuit whose temperature can be permitted to rise without exceeding the overall failure rate, thereby permitting implementation of a cooling system with a reduced heat dissipation factor.

Abstract: Power is dynamically conserved in a device by analyzing past processing performance of the device and predicting the amount of power required for future execution. In an example embodiment, a video frame is analyzed to determine what portion of the video frame was needed to render data. If less than the full video frame was needed, at least one power conservation technique is applied to the device for subsequent rendering of data. Power conservation techniques include adjusting the operating frequency of circuitry utilized to render data, adjusting the voltage applied to circuitry utilized to render data, and/or turning off/on circuitry utilized to render data.

Abstract: Power is dynamically conserved in a device by analyzing past processing performance of the device and predicting the amount of power required for future execution. In an example embodiment, a video frame is analyzed to determine what portion of the video frame was needed to render data. If less than the full video frame was needed, at least one power conservation technique is applied to the device for subsequent rendering of data. Power conservation techniques include adjusting the operating frequency of circuitry utilized to render data, adjusting the voltage applied to circuitry utilized to render data, and/or turning off/on circuitry utilized to render data.

Abstract: An access control device inhibits data transfers on a bus between unauthorized initiator-target pairs. A permission-matrix is maintained that identifies the access permission of each initiator relative to each target. The access device monitors the bus and determines the identification of the initiator and the intended target. If the initiator has the appropriate access rights to the target, the bus communication is permitted to occur, otherwise the communication is blocked, and an error signal is asserted. To provide further security, the identifier of initiators that are local to the access control device are communicated to the access control device via a direct wired connection to each initiator.

Abstract: A clock module operates in conjunction with the generation of the bus-clock signal to provide a combination of module-clocks that can be relied upon to provide an adequate safety margin for data transfers among processing modules at the speed of the bus-clock. In a preferred embodiment, a system-clock generates the bus-clock and a sample-clock, the sample-clock having a predetermined phase relationship with respect to the bus-clock. Base-clocks at each of the frequencies required for each processing module are generated in the conventional manner, and, in accordance with this invention, are sampled by the sample-clock to produce sampled module-clocks that are provided to each corresponding processing module. By sampling each base-clock with a sample-clock that has a corresponding predetermined phase relationship with respect to the bus-clock, each module-clock will have a predetermined phase relationship with respect to the bus-clock.

Abstract: A system architecture and method allows for both synchronous and asynchronous communications on a common bus. Components that are able to reliably communicate via the bus using a synchronous interface are configured to communicate synchronously. Components that would require an unacceptable reduction in system-clock frequency to achieve synchronous communications are configured to communicate asynchronously. A bus controller facilitates bus arbitration, as well as synchronous-to-synchronous, synchronous-to-asynchronous and asynchronous-to-synchronous, and asynchronous-to-asynchronous transfers between components. To accommodate for physical layout dependencies, the components include a bus interface that is configurable for either synchronous or asynchronous communications, so that the determination of whether communications will be synchronous or asynchronous can be made after the layout is completed.

Abstract: An integrated circuit includes a serpentine conductor track extending through a plurality of conductor layers and having ends coupled to first and second circuit elements, the ends being in opposing outermost ones of the conductor layers. The serpentine conductor track can selectively be made to be (i) continuous and electrically couple the first and second circuit elements together or (ii) discontinuous so that the first and second conductor elements are not electrically coupled. In the latter case, the discontinuity can be formed in any one of the conductor layers and a bridging conductor track is further formed in that one conductor layer which is coupled to the serpentine conductor track and which bypasses either of the first and second circuit elements. This structure has the advantage that circuit changes can be made in any conductor layer.

Abstract: A reset module operates in conjunction with a system clock module to provide a combination of reset and clock assertions that can be relied upon to reset conventional processing modules having a variety of reset architectures. A reset command initiates an assertion of the reset signal and an activation of all clocks at the system level. After a predetermined number of clock cycles, the system level clocks are deactivated, and then the reset signal is de-asserted. By providing multiple clock cycles with the reset signal asserted, processing modules having either asynchronous and synchronous reset will be reset. By disabling the clocks before de-asserting the reset signal, the likelihood of a timing hazard caused by an interaction of the reset signal and a clocking signal is reduced or eliminated.

Abstract: A clock module operates in conjunction with the generation of the bus-clock signal to provide a combination of module-clocks that can be relied upon to provide an adequate safety margin for data transfers among processing modules at the speed of the bus-clock. In a preferred embodiment, a system-clock generates the bus-clock and a sample-clock, the sample-clock having a predetermined phase relationship with respect to the bus-clock. Base-clocks at each of the frequencies required for each processing module are generated in the conventional manner, and, in accordance with this invention, are sampled by the sample-clock to produce sampled module-clocks that are provided to each corresponding processing module. By sampling each base-clock with a sample-clock that has a corresponding predetermined phase relationship with respect to the bus-clock, each module-clock will have a predetermined phase relationship with respect to the bus-clock.

Abstract: A clock module operates in conjunction with the generation of the bus-clock signal to provide a combination of module-clocks that can be relied upon to provide an adequate safety margin for data transfers among processing modules at the speed of the bus-clock. In a preferred embodiment, a system-clock generates the bus-clock and a sample-clock, the sample-clock having a predetermined phase relationship with respect to the bus-clock. Base-clocks at each of the frequencies required for each processing module are generated in the conventional manner, and, in accordance with this invention, are sampled by the sample-clock to produce sampled module-clocks that are provided to each corresponding processing module. By sampling each base-clock with a sample-clock that has a corresponding predetermined phase relationship with respect to the bus-clock, each module-clock will have a predetermined phase relationship with respect to the bus-clock.

Abstract: A method of manufacturing an integrated circuit having metal programmable logic cells. Metal programmable logic cells include transistors which, by varying routing of conductors in the metalization of the integrated circuit, may be connected in or disconnected from a logic path extending between the input and output of the cell. Transistors which are deselected by not being connected in the logic path are also decoupled from the supply rails. Generally speaking, deselected transistors can not be scan tested without substantial additional circuitry, as they do not form part of the logic path between the cell input and output to which the scan test circuitry is normally coupled. Decoupling transistors which are not in the logic path ensures that “stuck on” faults, in which transistors are stuck in a conductive state, do not allow current to flow between the supply rails through these faulty transistors, thus avoiding hot spots and reliability problems.

Abstract: The operands of an N×M bit multiplication are partitioned into N/j+1 and M/k+1 bit signed submultiples. The most significant submultiple is assigned the sign of the operand, while each of the less significant submultiples is assigned a positive sign. The product of each submultiple pair is sign extended to the width of the product (N+M), and the accumulation of these sign extended submultiple products provides the product of the original twos complement operands, in twos complement form.

Abstract: An integrated circuit includes a serpentine conductor track extending through a plurality of conductor layers and having ends coupled to first and second circuit elements, the ends being in opposing outermost ones of the conductor layers. The serpentine conductor track can selectively be made to be (i) continuous and electrically couple the first and second circuit elements together or (ii) discontinuous so that the first and second conductor elements are not electrically coupled. In the latter case, the discontinuity can be formed in any one of the conductor layers and a bridging conductor track is further formed in that one conductor layer which is coupled to the serpentine conductor track and which bypasses either of the first and second circuit elements. This structure has the advantage that circuit changes can be made in any conductor layer.

Abstract: An integrated circuit includes a serpentine conductor track extending through a plurality of conductor layers and having ends coupled to first and second circuit elements, the ends being in opposing outermost ones of the conductor layers. The serpentine conductor track can selectively be made to be (i) continuous and electrically couple the first and second circuit elements together or (ii) discontinuous so that the first and second conductor elements are not electrically coupled. In the latter case, the discontinuity can be formed in any one of the conductor layers and a bridging conductor track is further formed in that one conductor layer which is coupled to the serpentine conductor track and which bypasses either of the first and second circuit elements. This structure has the advantage that circuit changes can be made in any conductor layer.