Patents by Inventor Rung-Yuan Lee

Rung-Yuan Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10475744
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate, an isolation structure, an outer structure, and a gate structure. The isolation structure is disposed on the substrate. The outer structure surrounds a sidewall of the isolation structure. The gate structure surrounds a central part of the outer structure, so that the central part covered by the gate structure becomes a channel region, and the outer structure at both sides of the central part respectively becomes a source region and a drain region.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: November 12, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Kuan-Hung Chen, Rung-Yuan Lee, Chun-Tsen Lu
  • Patent number: 10403715
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a semiconductor nanowire, a gate structure, a first metal nanowire and a second metal nanowire. The semiconductor nanowire is disposed vertically on the substrate. The gate structure surrounds a middle portion of the semiconductor nanowire. The first metal nanowire is located on a side of the semiconductor nanowire and is electronically connected to a lower portion of the semiconductor nanowire. The second metal nanowire is located on the other side of the semiconductor nanowire and is electronically connected to the gate structure.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: September 3, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Rung-Yuan Lee, Chun-Tsen Lu, Kuan-Hung Chen
  • Patent number: 10396171
    Abstract: The present invention provides a method for forming a semiconductor structure, including the following steps: first, a substrate is provided, an interlayer dielectric (ILD) is formed on the substrate, a first dummy gate is formed in the ILD, wherein the first dummy gate includes a dummy gate electrode and two spacers disposed on two sides of the dummy gate electrode respectively. Next, two contact holes are formed in the ILD at two sides of the first dummy gate respectively. Afterwards, the dummy gate electrode is removed, so as to form a gate recess in the ILD, a first material layer is filled in the gate recess and a second material layer is filled in the two contact holes respectively, and an anneal process is performed on the first material layer and the second material layer, to bend the two spacers into two inward curving spacers.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: August 27, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung, Rung-Yuan Lee, Chih-Wei Yang
  • Publication number: 20190140051
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a semiconductor nanowire, a gate structure, a first metal nanowire and a second metal nanowire. The semiconductor nanowire is disposed vertically on the substrate. The gate structure surrounds a middle portion of the semiconductor nanowire. The first metal nanowire is located on a side of the semiconductor nanowire and is electronically connected to a lower portion of the semiconductor nanowire. The second metal nanowire is located on the other side of the semiconductor nanowire and is electronically connected to the gate structure.
    Type: Application
    Filed: December 17, 2018
    Publication date: May 9, 2019
    Applicant: United Microelectronics Corp.
    Inventors: Rung-Yuan Lee, Chun-Tsen Lu, Kuan-Hung Chen
  • Publication number: 20190081150
    Abstract: The present invention provides a method for forming a semiconductor structure, including the following steps: first, a substrate is provided, an interlayer dielectric (ILD) is formed on the substrate, a first dummy gate is formed in the ILD, wherein the first dummy gate includes a dummy gate electrode and two spacers disposed on two sides of the dummy gate electrode respectively. Next, two contact holes are formed in the ILD at two sides of the first dummy gate respectively. Afterwards, the dummy gate electrode is removed, so as to form a gate recess in the ILD, a first material layer is filled in the gate recess and a second material layer is filled in the two contact holes respectively, and an anneal process is performed on the first material layer and the second material layer, to bend the two spacers into two inward curving spacers.
    Type: Application
    Filed: November 1, 2018
    Publication date: March 14, 2019
    Inventors: En-Chiuan Liou, Yu-Cheng Tung, Rung-Yuan Lee, Chih-Wei Yang
  • Publication number: 20190074250
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate, an isolation structure, an outer structure, and a gate structure. The isolation structure is disposed on the substrate. The outer structure surrounds a sidewall of the isolation structure. The gate structure surrounds a central part of the outer structure, so that the central part covered by the gate structure becomes a channel region, and the outer structure at both sides of the central part respectively becomes a source region and a drain region.
    Type: Application
    Filed: October 6, 2017
    Publication date: March 7, 2019
    Applicant: United Microelectronics Corp.
    Inventors: Kuan-Hung Chen, Rung-Yuan Lee, Chun-Tsen Lu
  • Patent number: 10204986
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a semiconductor nanowire, a gate structure, a first metal nanowire and a second metal nanowire. The semiconductor nanowire is disposed vertically on the substrate. The gate structure surrounds a middle portion of the semiconductor nanowire. The first metal nanowire is located on a side of the semiconductor nanowire and is electronically connected to a lower portion of the semiconductor nanowire. The second metal nanowire is located on the other side of the semiconductor nanowire and is electronically connected to the gate structure.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: February 12, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Rung-Yuan Lee, Chun-Tsen Lu, Kuan-Hung Chen
  • Patent number: 10153353
    Abstract: The present invention provides a method for forming a semiconductor structure, including the following steps: first, a substrate is provided, an interlayer dielectric (ILD) is formed on the substrate, a first dummy gate is formed in the ILD, wherein the first dummy gate includes a dummy gate electrode and two spacers disposed on two sides of the dummy gate electrode respectively. Next, two contact holes are formed in the ILD at two sides of the first dummy gate respectively. Afterwards, the dummy gate electrode is removed, so as to form a gate recess in the ILD, a first material layer is filled in the gate recess and a second material layer is filled in the two contact holes respectively, and an anneal process is performed on the first material layer and the second material layer, to bend the two spacers into two inward curving spacers.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: December 11, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung, Rung-Yuan Lee, Chih-Wei Yang
  • Publication number: 20180350934
    Abstract: The present invention provides a method for forming a semiconductor structure, including the following steps: first, a substrate is provided, an interlayer dielectric (ILD) is formed on the substrate, a first dummy gate is formed in the ILD, wherein the first dummy gate includes a dummy gate electrode and two spacers disposed on two sides of the dummy gate electrode respectively. Next, two contact holes are formed in the ILD at two sides of the first dummy gate respectively. Afterwards, the dummy gate electrode is removed, so as to form a gate recess in the ILD, a first material layer is filled in the gate recess and a second material layer is filled in the two contact holes respectively, and an anneal process is performed on the first material layer and the second material layer, to bend the two spacers into two inward curving spacers.
    Type: Application
    Filed: June 5, 2017
    Publication date: December 6, 2018
    Inventors: En-Chiuan Liou, Yu-Cheng Tung, Rung-Yuan Lee, Chih-Wei Yang
  • Patent number: 10043718
    Abstract: A method of fabricating a semiconductor device includes the following steps: providing a semiconductor substrate having a fin structure thereon; forming a recess in the fin structure so that the semiconductor substrate is partially exposed from the bottom surface of the recess; forming a dopant source layer conformally disposed on side surfaces and a bottom surface of the recess; removing the dopant source layer disposed on the bottom surface of the recess until portions of the semiconductor substrate are exposed from the bottom surface of the recess; and annealing the dopant source layer so as to form a side doped region in the fin structure.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: August 7, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuan-Hung Chen, Rung-Yuan Lee, Chun-Tsen Lu, Chorng-Lih Young
  • Patent number: 10043807
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a plural fin structures, two gates, a protection layer and an interlayer dielectric layer. The fin structures are disposed on a substrate. The two gates are disposed on the substrate across the fin structures. The protection layer is disposed on the substrate, surrounded sidewalls of the two gates. The interlayer dielectric layer is disposed on the substrate, covering the fin structures and the two gates.
    Type: Grant
    Filed: July 4, 2017
    Date of Patent: August 7, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Rung-Yuan Lee, Yu-Cheng Tung, Chun-Tsen Lu, En-Chiuan Liou, Kuan-Hung Chen
  • Patent number: 9673053
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first material layer on the substrate; forming a stop layer on the first material layer; forming a second material layer on the stop layer; and performing a planarizing process to remove the second material layer, the stop layer, and part of the first material layer for forming a gate layer.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: June 6, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Rung-Yuan Lee, Yu-Ting Li, Jing-Yin Jhang, Chen-Yi Weng, Jia-Feng Fang, Yi-Wei Chen, Wei-Jen Wu, Po-Cheng Huang, Fu-Shou Tsai, Kun-Ju Li, Wen-Chin Lin, Chih-Chien Liu, Chih-Hsun Lin, Chun-Yuan Wu
  • Patent number: 9530871
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon; forming an epitaxial layer on the fin-shaped structure; forming a first contact etch stop layer (CESL) on the epitaxial layer; forming a source/drain region in the epitaxial layer; and forming a second CESL on the first CESL.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: December 27, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Yueh Tsai, Jia-Feng Fang, Yi-Wei Chen, Jing-Yin Jhang, Rung-Yuan Lee, Chen-Yi Weng, Wei-Jen Wu
  • Patent number: 9443757
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon; forming an epitaxial layer on the fin-shaped structure; forming a first contact etch stop layer (CESL) on the epitaxial layer; forming a source/drain region in the epitaxial layer; and forming a second CESL on the first CESL.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: September 13, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Yueh Tsai, Jia-Feng Fang, Yi-Wei Chen, Jing-Yin Jhang, Rung-Yuan Lee, Chen-Yi Weng, Wei-Jen Wu
  • Publication number: 20160148816
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first material layer on the substrate; forming a stop layer on the first material layer; forming a second material layer on the stop layer; and performing a planarizing process to remove the second material layer, the stop layer, and part of the first material layer for forming a gate layer.
    Type: Application
    Filed: November 20, 2014
    Publication date: May 26, 2016
    Inventors: Rung-Yuan Lee, Yu-Ting Li, Jing-Yin Jhang, Chen-Yi Weng, Jia-Feng Fang, Yi-Wei Chen, Wei-Jen Wu, Po-Cheng Huang, Fu-Shou Tsai, Kun-Ju Li, Wen-Chin Lin, Chih-Chien Liu, Chih-Hsun Lin, Chun-Yuan Wu